IP Library Granted Patent US 12,368,142
Granted Patent B2
US 12,368,142 · App. 17/826,780 · Granted Jul 22, 2025

Double side integration semiconductor package and method of forming the same

Inventors: Monsen Liu (Hsinchu, TW); Shang-Lun Tsai (Hsinchu, TW); Shuo-Mao Chen (New Taipei, TW); Shin-Puu Jeng (Po-Shan Village, TW)
Assignee: Taiwan Semiconductor Manufacturing Company Limited
H01L25/162H01L23/481H01L23/49816H01L23/49833H01L23/49838H01L24/16H01L25/167H01L21/4853H01L25/165H01L2224/16148H01L2224/16227H01L2224/16238H01L2924/1427H01L2924/1434H01L2924/16152H01L2924/16251H01L2924/182H01L2924/183
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,368,142
App. No.
17/826,780
Granted
Jul 22, 2025
Kind
B2
Abstract

An embodiment semiconductor device includes a first die package component, a second interposer electrically coupled to a first side of the first die package component, a third interposer having a voltage regulator circuit electrically coupled to a second side of the first die package component, and an optical component and a high-bandwidth-memory die, each electrically coupled to the second interposer. The first die package component may further include a double-sided semiconductor die, such that a first side of the double-sided semiconductor die is electrically coupled to the second interposer, and a second side of the double-sided semiconductor die is electrically coupled to the third interposer. The first die package component may further include a molding material and a through-molding-via formed in the molding material, such that the through-molding-via provides an electrical connection between the second interposer and the third interposer that bypasses the double-sided semiconductor die.

Claims (47)

1. A method of fabricating a semiconductor device, comprising:

forming a first die package component as an active double-sided interposer;

attaching a second interposer to a first side of the first die package component such that the second interposer is electrically coupled to the first die package component;

attaching an optical component to the second interposer such the optical component is electrically coupled to the second interposer, wherein the optical component includes an optical fiber;

forming a third interposer as an active interposer having a voltage regulator circuit;

attaching the third interposer to a second side of the first die package component such that the third interposer is electrically coupled to the first die package component; and

attaching a package lid such that the package lid is covering a surface of the second interposer opposite to the first die package component and includes an opening such that the optical fiber extends through the opening.

2. The method of claim 1 , wherein forming the first die package component further comprises:

forming a double-sided semiconductor die having electrical connections on opposite sides of the double-sided die;

forming a molding material that supports the double-sided semiconductor die; and

forming a through-molding-via in the molding material,

wherein the through-molding-via is configured to provide an electrical connection between the second interposer and the third interposer that bypasses the double-sided semiconductor die.

3. The method of claim 1 , further comprising attaching a high-bandwidth-memory die to the second interposer such that the high-bandwidth-memory die is electrically coupled to the second interposer.

4. The method of claim 1 , further comprising attaching a package substrate to the third interposer such that the third interposer is electrically coupled to the package substrate, wherein the third interposer is configured to receive electrical power from the package substrate.

5. The method of claim 4 , wherein the package lid is attached to the package substrate.

6. The method of claim 4 , further comprising forming a thermal interface material between the optical component and a surface of the package substrate.

7. The method of claim 1 , further comprising mounting one or more substrate mounted devices to the third interposer such that the third interposer is electrically coupled to the one or more substrate mounted devices, wherein the one or more substrate mounted devices comprise a capacitor, an inductor, or a resistor.

8. A method of fabricating a semiconductor device, comprising:

forming a first die package component as an active double-sided interposer;

attaching a second interposer to a first side of the first die package component such that the second interposer is electrically coupled to the first die package component;

forming a third interposer as an active interposer; and

attaching the third interposer to a second side of the first die package component such that the third interposer is electrically coupled to the first die package component,

wherein the second interposer and third interposer are electrically connected by a through-molding-via located within the first die package.

9. The method of claim 8 , wherein forming the first die package component further comprises:

forming a double-sided semiconductor die having electrical connections on opposite sides of the double-sided die;

forming a molding material; and

forming a through-molding-via in the molding material.

10. The method of claim 8 , further comprising attaching a high-bandwidth-memory die to the second interposer such that the high-bandwidth-memory die is electrically coupled to the second interposer.

11. The method of claim 8 , further comprising attaching an optical component to the second interposer such that the optical component is electrically coupled to the second interposer.

12. The method of claim 8 , further comprising attaching a package substrate to the third interposer such that the third interposer is electrically coupled to the package substrate.

13. The method of claim 12 , further comprising attaching a package lid to the package substrate such that the package lid is covering a surface of the second interposer opposite to the first die package component.

14. The method of claim 8 , further comprising mounting one or more substrate mounted devices to the third interposer such that the third interposer is electrically coupled to the one or more substrate mounted devices, wherein the one or more substrate mounted devices comprise a capacitor, an inductor, or a resistor.

15. A method of fabricating a semiconductor device, comprising:

forming a first die package component, comprising:

forming a semiconductor die;

forming a molding material that supports the semiconductor die; and

forming a through-molding-via in the molding material;

attaching a second interposer to a first side of the first die package component; and

attaching a third interposer to a second side of the first die package component; and

attaching a package substrate to the third interposer,

wherein the second interposer and the third interposer are electrically coupled to the first die package component and the package substrate is electrically coupled to the third interposer,

wherein the through-molding-via is configured to provide an electrical connection between the second interposer and the third interposer.

16. The method of claim 15 , further comprising attaching a high-bandwidth-memory die to the second interposer such that the high-bandwidth-memory die is electrically coupled to the second interposer.

17. The method of claim 15 , further comprising attaching an optical component to the second interposer such that the optical component is electrically coupled to the second interposer.

18. The method of claim 15 , further comprising attaching a package substrate to the third interposer such that the third interposer is electrically coupled to the package substrate.

19. The method of claim 18 , further comprising attaching a package lid to the package substrate such that the package lid is covering a surface of the second interposer opposite to the first die package component.

20. The method of claim 15 , further comprising mounting one or more substrate mounted devices to the third interposer such that the third interposer is electrically coupled to the one or more substrate mounted devices, wherein the one or more substrate mounted devices comprise a capacitor, an inductor, or a resistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2022
From: LIU, MONSEN; TSAI, SHANG-LUN; CHEN, SHUO-MAO; JENG, SHIN-PUU
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Reel/Frame 060039/0348 →
Continuity (1)
Related Publication 20230402438A1 · Dec 14, 2023
References Cited (16)
US 20060092610A1 · Hegde · 2006 [cited by examiner]
US 20190148342A1 · Hu · 2019 [cited by examiner]
US 20220013445A1 · Kim · 2022 [cited by examiner]
US 20230098957A1 · Eid · 2023 [cited by examiner]
US 20230109629A1 · Sato · 2023 [cited by examiner]
US 20230298964A1 · Salama · 2023 [cited by examiner]
TW 201432871A · 2014 [cited by applicant]
TW 202002052A · 2020 [cited by applicant]
TW 202114492A · 2021 [cited by applicant]
TW 202117945A · 2021 [cited by applicant]
TW 202134713A · 2021 [cited by applicant]
TW 202139373A · 2021 [cited by applicant]
TW 202147545A · 2021 [cited by applicant]
TW 202205560A · 2022 [cited by applicant]
TW 202220131A · 2022 [cited by applicant]
Taiwanese Patent and Trademark Office; TW application No. 112108494; Office Action mailed Feb. 29, 2024, 24 pages. [cited by applicant]