IP Library › Granted Patent US 11,803,508
Granted Patent B2
US 11,803,508 · App. 17/873,585 · Granted Oct 31, 2023

Systems and methods for implementing a machine perception and dense algorithm integrated circuit and enabling a flowing propagation of data within the integrated circuit

Inventors: Nigel Drego (Burlingame, CA); Aman Sikka (Burlingame, CA); Ananth Durbha (Burlingame, CA); Mrinalini Ravichandran (Burlingame, CA); Robert Daniel Firu (Burlingame, CA); Veerbhan Kheterpal (Burlingame, CA)
Assignee: quadric.io, Inc.
G06F15/8046G06F9/30032G06F9/5061G06F30/39
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,803,508
App. No.
17/873,585
Granted
Oct 31, 2023
Kind
B2
Abstract

Systems and methods of propagating data within an integrated circuit includes: identifying a coarse data propagation path for distinct subsets of data of an input dataset that includes: setting inter-core data movements for the distinct subsets of data, the inter-core data movements defining a predetermined propagation of a given subset of data between two or more of a plurality of cores of an integrated circuit array of the integrated circuit; identifying a granular data propagation path for each distinct subset of data that includes: setting intra-core data movements for each distinct subset of data, the intra-core data movements defining a predetermined propagation of the given subset of data within one or more of the plurality of cores of the integrated circuit array of the integrated circuit; enabling a flow of the input dataset within the integrated circuit based on the coarse data propagation path and the granular propagation path.

Claims (65)

1. A method for moving a plurality of datasets within a processing core of an integrated circuit, the method comprising:

storing each of a plurality of distinct datasets at a register file of one of a plurality of distinct data ports of a processing core of an array of processing cores; and

executing data movement instructions that, when executed, move the plurality of datasets rotationally within the processing core, the plurality of distinct data ports include (a) a North data port along a first side, (b) an East data port along a second side, (c) a South data port along a third side, and (d) a West data port along a fourth side,

wherein executing the data movement instructions includes:

moving each of the plurality of datasets stored within the plurality of distinct data ports of the processing core, in a rotation, from a starting data port of the plurality of distinct data ports to a terminal data port of the plurality of distinct data ports of the processing core,

wherein:

the starting data port is one of the North data port, the East data port, the South data port, and the West data port, and

the terminal data port is distinct from the starting data port and is one of the North data port, the East data port, the South data port, and the West data port.

2. The method according to claim 1 , wherein:

(i) the data movement instructions include a sequence of discrete data rotation instructions, and

(ii) each discrete data rotation instruction of the sequence comprises a rotational movement value that is a degree of rotation between zero and three hundred sixty.

3. The method according to claim 2 , wherein

(iii) each discrete data rotation instruction of the sequence is associated with a required movement of a dataset within a plurality of distinct processing cores of the array of processing cores, and

(iv) executing the data movement instructions causes the dataset to rotate between data ports of each of the plurality of distinct processing cores.

4. The method according to claim 1 , wherein

(i) the data movement instructions include instructions for moving a dataset directly from a data port of a distinct processing core that neighbors the processing core to the starting data port of the processing core, and

(ii) executing the data movement instructions causes an entry of the dataset into the processing core via a transmission of the dataset from the port of the distinct processing core directly to the starting data port of the processing core.

5. The method according to claim 1 , wherein

(i) the data movement instructions include instructions for moving a dataset directly from a data loading controller of the integrated circuit that neighbors the processing core to the starting data port of the processing core, and

(ii) executing the data movement instructions causes an entry of the dataset into the processing core via an injection of the dataset from the data loading controller directly to the starting data port of the processing core.

6. The method according to claim 1 , wherein

(i) the data movement instructions include instructions for moving a dataset directly from the terminal data port of the processing core to a data port of a distinct processing core that neighbors the processing core, and

(ii) executing the data movement instructions causes an exit of the dataset from the processing core via a transmission of the dataset from the terminal data port of the processing core directly to the data port of the distinct processing core.

7. The method according to claim 1 , wherein:

(i) the data movement instructions include instructions for moving a dataset directly from the starting data port of the processing core to a data loading controller of the integrated circuit that neighbors the processing core, and

(ii) executing the data movement instructions causes an exit of the dataset from the processing core via a transmission of the dataset from the terminal data port of the processing core directly to the data loading controller.

8. The method according to claim 1 , wherein

(i) the data movement instructions include instructions for moving a dataset from the starting data port of the processing core through an intermediary within the processing core to the terminal data port of the processing core, and

(ii) executing the data movement instructions causes a movement of the dataset from the starting data port via the intermediary to the terminal data port of the processing core.

9. The method according to claim 8 , wherein

the intermediary of the processing core comprises a main register file arranged within the processing core.

10. The method according to claim 1 , wherein

the processing core comprises a plurality of processing circuits arranged within the processing core.

11. The method according to claim 10 , wherein

(i) the data movement instructions include instructions for moving a dataset from between one or more of the plurality of distinct data ports of the processing core and one or more of the plurality of processing circuits of the processing core.

12. The method according to claim 10 , wherein

the plurality of processing circuits of the processing core comprise a plurality of matrix multiply accumulators.

13. A method for moving a plurality of datasets within a processing core of an integrated circuit, the method comprising:

executing data movement instructions that, when executed, move a plurality of distinct datasets rotationally within a processing core of an array of processing cores, the processing core comprising a plurality of distinct processing circuits arranged along sides of the processing core, the plurality of distinct processing circuits include (a) a North processing circuit along a first side, (b) an East processing circuit along a second side, (c) a South processing circuit along a third side, and (d) a West processing circuit along a fourth side,

wherein executing the data movement instructions include:

moving each of the plurality of datasets, in a rotation, from a starting data port of the plurality of distinct processing circuits to a terminal processing circuit of the plurality of distinct processing circuits of the processing core,

wherein:

the starting processing circuit is one of the North processing circuit, the East processing circuit, the South processing circuit, and the West processing circuit, and

the terminal processing circuit is distinct from the starting processing circuit and is one of the North processing circuit, the East processing circuit, the South processing circuit, and the West processing circuit.

14. The method according to claim 13 , wherein

the plurality of processing circuits of the processing core comprise a plurality of matrix multiply accumulators.

15. The method according to claim 13 , wherein:

(i) the data movement instructions include a sequence of discrete data rotation instructions, and

(ii) each discrete data rotation instruction of the sequence comprises a rotational movement value that is a degree of rotation between zero and three hundred sixty.

16. The method according to claim 15 , wherein

(iii) each discrete data rotation instruction of the sequence is associated with a required movement of a dataset within a plurality of distinct processing cores of the array of processing cores, and

(iv) executing the data movement instructions causes the dataset to rotate between processing circuits of each of the plurality of distinct processing cores.

17. A system for moving a dataset within a processing core of an integrated circuit, the system comprising:

an array of processing cores; and

an instructions generating circuit that produces data movement instructions that, when executed, move a plurality of distinct datasets rotationally within a processing core of the array of processing cores, the processing core comprising a plurality of distinct data ports that include (a) a North data port along a first side, (b) an East data port along a second side, (c) a South data port along a third side, and (d) a West data port along a fourth side,

wherein each of the plurality of distinct data ports includes a register file,

wherein executing the data movement instructions include:

moving each of the plurality of datasets stored within the register files of the plurality of distinct data ports of the processing core, in a rotation, from a starting of the plurality of distinct data ports to a terminal data port of the plurality of distinct data ports of the processing core,

wherein:

the starting is one of the North data port, the East data port, the South data port, and the West data port, and

the terminal data port is distinct from the starting and is one of the North data port, the East data port, the South data port, and the West data port.

18. The system according to claim 17 , wherein:

the instructions generating circuit produces the data movement instructions that include a sequence of discrete data rotation instructions, wherein each discrete data rotation instruction of the sequence comprises a rotational movement value that is a degree of rotation between zero and three hundred sixty.

19. The method according to claim 1 , wherein:

executing the data movement instructions includes executing a plurality of data rotation instructions for rotating each of a plurality of a plurality of data subsets in a single clock cycle.

Assignments (2)
SECURITY INTEREST Recorded Apr 3, 2025
From: QUADRIC, INC.
To: DECATHLON ALPHA V, L.P.
Reel/Frame 070722/0441 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2022
From: DREGO, NIGEL; SIKKA, AMAN; DURBHA, ANANTH; RAVICHANDRAN, MRINALINI; FIRU, ROBERT DANIEL; KHETERPAL, VEERBHAN
To: QUADRIC.IO, INC.
Reel/Frame 060638/0014 →
Continuity (4)
Continuation 17222847 · Apr 5, 2021
Continuation 16292537 · Mar 5, 2019
Provisional Application 62649551 · Mar 28, 2018
Related Publication 20220358081A1 · Nov 10, 2022