IP Library Granted Patent US 12,487,283
Granted Patent B2
US 12,487,283 · App. 17/874,294 · Granted Dec 2, 2025

Information processing apparatus and information processing method

Inventor: Tsutomu Nagaoka (Kanagawa, JP)
Assignee: FUJIFILM Business Innovation Corp.
G01R31/3177G01R31/31705G01R31/318519
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Quick Facts
Patent No.
US 12,487,283
App. No.
17/874,294
Granted
Dec 2, 2025
Kind
B2
Abstract

An information processing apparatus includes an integrated circuit that is capable of reconfiguring a logic circuit, that executes data processing, and that is capable of acquiring signal data from an acquisition target position set in a circuit portion where the data processing is performed and outputting the signal data, a change unit that changes the acquisition target position in the circuit portion where the data processing of the integrated circuit is performed in a case where an error is generated in the data processing of the integrated circuit, and a control unit that causes the integrated circuit to re-execute the data processing in which the error is generated, after the acquisition target position is changed.

Claims (32)

1 . An information processing apparatus comprising:

an integrated circuit that is capable of reconfiguring a logic circuit, that executes data processing, and that is capable of acquiring signal data from an acquisition target position set in an input and an output of a circuit component where the data processing is performed and outputting the signal data; and

a processor configured to:

change the acquisition target position in the circuit component where the data processing of the integrated circuit is performed in a case where an error is generated in the data processing of the integrated circuit; and

cause the integrated circuit to re-execute the data processing in which the error is generated, after the acquisition target position is changed.

2 . The information processing apparatus according to claim 1 ,

wherein the acquisition target position is set for each one or a plurality of predetermined areas in the integrated circuit and is changed within the area.

3 . The information processing apparatus according to claim 2 ,

wherein the processor is configured to initially set the acquisition target position at a location where the error is generated in the area that includes the location where the error is generated.

4 . The information processing apparatus according to claim 3 ,

wherein the processor is configured to set the acquisition target position at a preceding stage of a position before the change along a flow of data within the area.

5 . The information processing apparatus according to claim 1 ,

wherein the processor is configured to

initially set the acquisition target position at a location where the error is generated, and

set the acquisition target position at a preceding stage of a position before the change along a flow of data in the circuit component where the data processing is performed, after the integrated circuit is caused to re-execute the data processing.

6 . The information processing apparatus according to claim 1 ,

wherein the integrated circuit is capable of reconfiguring only an area set in the logic circuit by reading configuration data of the area, and

the processor is configured to read, out of the configuration data prepared for each of areas, configuration data of an area that includes a location where the error is generated and changes the acquisition target position provided in the area by reconfiguring the area that includes the location where the error is generated.

7 . The information processing apparatus according to claim 1 ,

wherein the processor is configured to re-execute the data processing in which the error is generated from a predetermined operation according to the data processing performed by the integrated circuit.

8 . The information processing apparatus according to claim 7 ,

wherein the data processing that is executed by the integrated circuit is image processing, and

the processor is configured to re-execute processing in which the error is generated for each unit image in an image that is a target of the image processing.

9 . An information processing apparatus comprising:

an integrated circuit that is capable of reconfiguring a logic circuit, that executes data processing, and that is capable of acquiring signal data from an acquisition target position set in an input and an output of a circuit component where the data processing is performed and outputting the signal data; and

a processor configured to:

reconfigure, in a case where an error is generated in the data processing of the integrated circuit, the logic circuit of the integrated circuit such that signal data is acquired from a position different from a previous position when the error is generated next time; and

cause the integrated circuit to re-execute the data processing in which the error is generated, after the logic circuit of the integrated circuit is reconfigured.

10 . An information processing method comprising:

executing data processing, via an integrated circuit that is capable of reconfiguring a logic circuit, by acquiring signal data from an acquisition target position set in an input and an output of a circuit component where the data processing is performed and outputting the signal data;

changing, by a processor, the acquisition target position in the circuit component where the data processing of the integrated circuit is performed in a case where an error is generated in the data processing of the integrated circuit; and

causing, by the processor, the integrated circuit to re-execute the data processing in which the error is generated, after the acquisition target position is changed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2022
From: NAGAOKA, TSUTOMU
To: FUJIFILM BUSINESS INNOVATION CORP.
Reel/Frame 060649/0089 →
Priority Claims (1)
JP 2022-053548 · Mar 29, 2022 · national
Continuity (1)
Related Publication 20230314507A1 · Oct 5, 2023
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