IP Library Granted Patent US 7,698,594
Granted Patent B2
US 7,698,594 · App. 11/622,738 · Granted Apr 13, 2010

Reconfigurable processor and reconfiguration method executed by the reconfigurable processor

Assignee: Canon Kabushiki Kaisha
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Quick Facts
Patent No.
US 7,698,594
App. No.
11/622,738
Granted
Apr 13, 2010
Kind
B2
Abstract

A reconfigurable processor which is capable of carrying out or continuing processing even after occurrence of an error in a data processing unit within the reconfigurable processor. The reconfigurable processor has a processing element matrix comprised of a plurality of processing elements. The reconfigurable processor reconfigures the processing element matrix according to an error of the processing element matrix.

Claims (31)

1. A reconfigurable processor comprising:

a processing element matrix having a plurality of data processing units; and

a reconfiguration unit that sets configuration information into said processing element matrix, such that a processing performed by one of the data processing units, and a connection between the one of the data processing units and another one of the data processing units are changed to:

substitute a faulty data processing unit with a non-faulty data processing unit among the data processing units;

carry out with the non-faulty data processing unit a processing that the faulty data processing unit was carrying out before becoming faulty;

route an input to the faulty data processing unit to the non-faulty data processing unit; and

route an output from the non-faulty data processing unit to an output to which the faulty data processing was connected before becoming faulty.

2. A reconfigurable processor as claimed in claim 1 , wherein said reconfiguration unit reconfigures said processing element matrix such that the faulty data processing unit does not affect the output of said processing element matrix.

3. A reconfigurable processor as claimed in claim 1 , each of said data processing units has a detection unit that detects an error thereof.

4. A reconfigurable processor as claimed in claim 1 , wherein said processing element matrix restarts processing after being reconfigured.

5. A reconfigurable processor as claimed in claim 1 , wherein said processing element matrix processes data read out from a storage device, and said reconfiguration unit determines a storage location of data to be processed by said processing element matrix after reconfiguration, in the storage device, according to progress of processing by said processing element matrix.

6. A method of reconfiguring a reconfigurable processor having a processing element matrix having a plurality of data processing units, the method comprising:

a detection step of detecting an error in each of the data processing units; and

a reconfiguration step of setting configuration information into the processing element matrix such that a processing performed by one of the data processing units, and a connection between the one of the data processing units and another one of the data processing units are changed to:

substitute a faulty data processing unit with a non-faulty data processing unit among the data processing units;

carry out with the non-faulty data processing a processing that the faulty data processing unit was carrying out before becoming faulty;

route an input to the faulty data processing unit to the non-faulty data processing unit; and

route an output from the non-faulty data processing unit to an output to which the faulty data processing was connected before becoming faulty.

7. A method as claimed in claim 6 , wherein said reconfiguration step reconfigures the processing element matrix such that the faulty data processing unit does not affect the output of the processing element matrix.

8. A method as claimed in claim 6 , further comprising the step of causing the processing element matrix to restart processing after being reconfigured.

9. A method as claimed in claim 6 , further comprising the step of determining a storage location of data to be processed by the processing element matrix after reconfiguration, according to progress of processing by the processing element matrix.

10. A computer-readable storage medium storing a computer program, that when executed by a computer, causes the computer to execute a method for reconfiguring a reconfigurable processor including a processing element matrix having a plurality of data processing units, the computer-readable storage medium being a floppy disk, a hard disk, an optical disk, a magnetic tape, a nonvolatile memory card, or a ROM, or being an equivalent of a floppy disk, a hard disk, an optical disk, a magnetic tape, a nonvolatile memory card, or a ROM, the computer program comprising:

a detection module for detecting an error in each of the processing devices; and

a reconfiguration module for setting configuration information into the processing element matrix such that a processing performed by one of the data processing units, and a connection between the one of the data processing units and another one of the data processing units are changed to:

substitute a faulty data processing unit with a non-faulty data processing unit among the data processing units;

carry out with the non-faulty data processing unit a processing that the faulty data processing unit was carrying out before becoming faulty;

route an input to the faulty data processing unit to the non-faulty data processing unit; and

route an output from the non-faulty data processing unit to an output to which the faulty data processing was connected before becoming faulty.

11. A computer-readable storage medium as claimed in claim 10 , wherein said reconfiguration module reconfigures the processing element matrix such that the faulty data processing unit does not affect the output of the processing element matrix.

12. A computer-readable storage medium as claimed in claim 10 , further comprising a restart module for causing the processing element matrix to restart processing after being reconfigured.

13. A computer-readable storage medium as claimed in claim 10 , further comprising a storage location determining module for determining a storage location of data to be processed by the processing element matrix after reconfiguration, according to progress of processing by the processing element matrix.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2007
From: AIZAWA, EIJI
To: CANON KABUSHIKI KAISHA
Reel/Frame 018753/0709 →
Priority Claims (1)
JP 2006-006295 · Jan 13, 2006 · national
Continuity (1)
Related Publication 20070180315A1 · Aug 2, 2007