IP Library Granted Patent US 11,784,210
Granted Patent B2
US 11,784,210 · App. 17/877,550 · Granted Oct 10, 2023

Light-emitting device and manufacturing method thereof

Inventors: Cheng-Yu Chen (Hsinchu, TW); Hui-Chun Yeh (Hsinchu, TW); Chien-Fu Shen (Hsinchu, TW)
Assignee: EPISTAR CORPORATION
H01L27/156H01L33/38
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Quick Facts
Patent No.
US 11,784,210
App. No.
17/877,550
Granted
Oct 10, 2023
Kind
B2
Abstract

A method for manufacturing a light-emitting device, includes: forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layer, a second semiconductor layer and an active region formed therebetween; removing portions of the semiconductor stack to form a plurality of mesas and exposing a part of the first semiconductor layer, wherein the part of the first semiconductor layer includes a first portion and a second portion; forming a plurality of trenches by removing the first portion of the part of the first semiconductor to exposing a top surface of the substrate and a side wall of the first semiconductor, wherein the plurality of trenches defining a plurality of light-emitting units in the semiconductor stack; wherein in a top view, the plurality of trenches includes a first trench extending along a first direction and a second trench extending along a second direction not parallel with the first trench; and wherein the second trench includes an end; forming connection electrodes on the semiconductor stack to electrically connect the adjacent light-emitting units; and separating the substrate and the second portion of the part of the first semiconductor layer along a first dicing line not parallel with the second direction; wherein the first dicing line intersects the end of the second trench.

Claims (27)

1. A method for manufacturing a light-emitting device, comprising:

forming a semiconductor stack on a substrate, wherein the semiconductor stack comprises a first semiconductor layer, a second semiconductor layer and an active region formed therebetween;

removing portions of the semiconductor stack to form a plurality of mesas and exposing a part of the first semiconductor layer, wherein the part of the first semiconductor layer comprises a first portion and a second portion;

forming a plurality of trenches by removing the first portion of the part of the first semiconductor to exposing a top surface of the substrate and a side wall of the first semiconductor, wherein the plurality of trenches defining a plurality of light-emitting units in the semiconductor stack;

wherein in a top view, the plurality of trenches comprises a first trench extending along a first direction and a second trench extending along a second direction not parallel with the first trench; and

wherein the second trench comprises an end;

forming connection electrodes on the semiconductor stack to electrically connect the adjacent light-emitting units; and

separating the substrate and the second portion of the part of the first semiconductor layer along a first dicing line not parallel with the second direction;

wherein the first dicing line intersects the end of the second trench.

2. The method according to claim 1 , wherein the end of the second trench is formed in the first semiconductor layer.

3. The method according to claim 1 , wherein after separating the substrate and the second portion of the part of the first semiconductor layer, a first side wall of the first semiconductor layer is exposed;

a second side wall of the substrate is exposed; and

wherein the first side wall connects to the second side wall.

4. The method according to claim 3 , wherein the first side wall and the second side wall are coplanar.

5. The method according to claim 1 , wherein an included angle between the side wall of the first semiconductor layer and the top surface of the substrate is between 20 degrees and 80 degrees.

6. The method according to claim 1 , further comprising forming an insulating layer on the plurality of trenches before forming the connection electrodes on the semiconductor stack.

7. The method according to claim 6 , wherein the substrate comprises a plurality of patterned structures on the top surface, and the insulating layer is conformably formed on the plurality of patterned structures in the plurality of trenches.

8. The method according to claim 7 , wherein the connection electrodes are conformably formed on the insulating layer in the plurality of trenches.

9. The method according to claim 1 , after separating the substrate and the second portion of the part of the first semiconductor layer into a firs piece and a second piece, the end of the second trench forms a notch in the first semiconductor layer of the first piece.

10. The method according to claim 9 , wherein the notch is located at an edge of the first piece.

11. The method according to claim 9 , wherein the notch comprises a maximum bottom width, the second trench comprises a minimum bottom width, and a difference between the maximum bottom width and the minimum bottom width is less than 20%.

12. The method according to claim 9 , wherein the notch comprises a first side wall and an included angle between the first side wall and the top surface is between 20 degrees and 80 degrees.

13. The method according to claim 1 , wherein after separating the substrate and the second portion of the part of the first semiconductor layer:

the plurality of light-emitting units comprises a first light-emitting unit and a second light-emitting unit adjacent to each other and one of the plurality of trenches is formed therebetween;

the side wall of the first semiconductor layer of the first light-emitting unit faces the second light-emitting unit and the first semiconductor layer of the first light-emitting unit further comprises a second sidewall not facing second light-emitting unit; and

the second sidewall is substantially perpendicular to a top surface of the substrate.

14. The method according to claim 1 , further comprising providing a laser on the substrate corresponding to the first dicing line to form a modified region inside the substrate.

Assignments (2)
CHANGE OF NAME Recorded Feb 26, 2026
From: EPISTAR CORPORATION
To: ENNOSTAR CORPORATION
Reel/Frame 075152/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2022
From: CHEN, CHENG-YU; YEH, HUI-CHUN; SHEN, CHIEN-FU
To: EPISTAR CORPORATION
Reel/Frame 060733/0019 →
Priority Claims (1)
TW 108131271 · Aug 30, 2019 · national
Continuity (2)
Continuation 17006459 · Aug 28, 2020
Related Publication 20220367563A1 · Nov 17, 2022