Memory device using semiconductor element
View Patent ↗An n + layer 3 a connected to a source line SL at both ends, an n + layer 3 b connected to a bit line BL, a first gate insulating layer 4 a formed on a semiconductor substrate 1 existing on an insulating film 2 , a gate conductor layer 16 a connected to a plate line PL, a gate insulating layer 4 b formed on the semiconductor substrate, and a second gate conductor layer 5 b connected to a word line WL and having a work function different from a work function of the gate conductor layer 16 a are disposed on the semiconductor substrate, and data hold operation of holding, near a gate insulating film, holes generated by an impact ionization phenomenon or gate-induced drain leakage current inside a channel region 12 of the semiconductor substrate 1 and data erase operation of removing the holes from inside the substrate 1 and the channel region 12 are performed by controlling voltage applied to the source line SL, the plate line PL, the word line WL, and the bit line BL.
1. A memory device using a semiconductor element, the memory device comprising:
a semiconductor substrate formed in a columnar shape having a first columnar portion located along a length of the semiconductor substrate near one end of the semiconductor substrate and a second columnar portion located, next to the first columnar portion, along the length of the semiconductor substrate near the other end of the semiconductor substrate;
a first gate insulating layer surrounding at least a part of a side surface of the first columnar portion of the semiconductor substrate;
a second gate insulating layer surrounding at least a part of a side surface of the second columnar portion of the semiconductor substrate;
a first gate conductor layer surrounding the first gate insulating layer;
a second gate conductor layer surrounding the second gate insulating layer, wherein the second gate conductor layer is not electrically connected to the first gate conductor layer and has a work function different from a work function of the first gate conductor layer;
a first impurity layer provided to one end of the semiconductor substrate on a side of the first columnar portion and a second impurity layer provided to the other end of the semiconductor substrate on a side of the second columnar portion;
wherein the first impurity layer, the second impurity layer, the first gate conductor layer and the second gate conductor layer are arranged such that voltages applied to the first impurity layer, the second impurity layer, the first gate conductor layer and the second gate conductor layer are controlled to (i) perform a memory write operation that generates a group of electrons and a group of holes in the semiconductor substrate by an impact ionization phenomenon caused by a current flowing between the first impurity layer and the second impurity layer or by gate-induced drain leakage current, and removes one of the group of electrons or the group of holes, which is minority carriers from the semiconductor substrate leaving, in locations within the semiconductor substrate contacting the first gate insulating layer and the second gate insulating layer, some or all of the other of the group of electrons or the group of holes, which are majority carriers in the semiconductor substrate, and
(ii) perform a memory erase operation that removes from the semiconductor substrate the other of the group of electrons or the group holes, which are the majority carriers in the semiconductor substrate.
2. The memory device using the semiconductor element according to claim 1 , wherein
one of the first or second impurity layer is connected with a source line, the other thereof is connected with a bit line, the first gate conductor layer is connected with a plate line, and the second gate conductor layer is connected with a word line,
the memory erase operation and the memory write operation are performed with voltages applied to the source line, the bit line, the plate line, and the word line, and
the majority carriers in the first impurity layer are electrons, the majority carriers in the semiconductor substrate are holes, and the work function of the first gate conductor layer is larger than the work function of the second gate conductor layer.
3. The memory device using the semiconductor element according to claim 1 , wherein
one of the first or second impurity layer is connected with a source line, the other thereof is connected with a bit line, the first gate conductor layer is connected with a plate line, and the second gate conductor layer is connected with a word line,
the memory erase operation and the memory write operation are performed with voltages applied to the source line, the bit line, the plate line, and the word line, and
the majority carriers in the first impurity layer are holes, the majority carriers in the semiconductor substrate are electrons, and the work function of the first gate conductor layer is smaller than the work function of the second gate conductor layer.
4. The memory device using the semiconductor element according to claim 1 , wherein the first gate conductor layer and the second gate conductor layer are overlapped with each other and the work functions of the first and second gate conductor layers are different from each other.