CBRAM BOTTOM ELECTRODE STRUCTURES

1 . A method of forming bottom electrodes in a resistive memory device, the method comprising:

a) depositing a bottom insulator on a substrate interlayer dielectric (ILD);

b) forming vias in the substrate ILD by patterning and etching holes in the bottom insulator and the substrate ILD;

c) filling the holes with a via metal to form a flat via surface;

d) depositing a bottom electrode thin film and a top insulator;

e) defining the bottom electrode;

f) etching the top insulator, the bottom electrode thin film, and the bottom insulator;

g) depositing a cell plate layer having a switching layer, an anode layer, and a cap layer;

h) patterning the cell plate layer by depositing and patterning a cell plate hard mask layer, and then etching the cell plate layer;

i) encapsulating the cell plate layer; and

j) forming electrical contact to the cell plate layer.

2 . The method of claim 1 , wherein the depositing the bottom insulator comprises a back end of line (BEOL) of a standard silicon process.

3 . The method of claim 1 , wherein the bottom insulator and the substrate are etched at a same time.

4 . The method of claim 1 , wherein the bottom insulator is etched using a first etch process, and the substrate is then etched using a second etch process.

5 . The method of claim 1 , wherein the defining the bottom electrodes comprises depositing and patterning a bottom electrode hard mask layer.

6 . The method of claim 5 , wherein a same thin film is used as both the top insulator and the bottom electrode hard mask layer.

7 . The method of claim 1 , wherein the switching layer comprises SiO 2 , the anode layer comprises Hf x Te 1-x , and the cap layer comprises Ta x Si 1-x .

8 . The method of claim 1 , wherein the cell plate layer covers one or more bottom electrodes.

9 . The method of claim 1 , wherein the encapsulating the cell plate layer comprises using an ILD layer.

10 . The method of claim 9 , wherein the making electrical contact to the cell plate layer comprises forming top contacts or vias through the ILD layer.

11 . The method of claim 1 , wherein a shape of each of the bottom electrodes is rounded.

12 . The method of claim 1 , wherein a shape of each of the bottom electrodes is rectangular or dumbbell.

13 . The method of claim 1 , wherein each of the bottom electrodes comprises a sidewall.

14 . A resistive memory device, comprising:

a) a bottom insulator on a substrate interlayer dielectric (ILD);

b) vias in the bottom insulator and the substrate ILD, the vias having a via metal and a flat via surface;

c) a bottom electrode fully covering the vias and at least a portion of the bottom insulator;

d) a top insulator on the bottom electrode;

e) a bottom electrode hard mask on the top insulator, wherein the bottom electrode hard mask is wider than the vias;

f) a cell plate layer in contact with the bottom electrode hard mask, the top insulator, the bottom electrode, the bottom insulator, and the substrate ILD; and

g) an electrical contact connected to the cell plate layer.

15 . The resistive memory device of claim 14 , wherein the switching layer comprises SiO 2 , the anode layer comprises Hf x Te 1-x , and the cap layer comprises Ta x Si 1-x .

16 . The resistive memory device of claim 14 , wherein each of the bottom electrodes comprises a sidewall.

17 . The resistive memory device of claim 14 , wherein the cell plate layer covers one or more bottom electrodes.

18 . The resistive memory device of claim 14 , wherein the cell plate layer is encapsulated by an ILD layer, and electrical contact to the cell plate layer is made by top contacts or vias through the ILD layer.

19 . The resistive memory device of claim 14 , wherein a shape of each of the bottom electrodes is rounded.

20 . The resistive memory device of claim 14 , wherein a shape of each of the bottom electrodes is rectangular or dumbbell.