Granted Patent B2

US 12,550,535 · App. 17/880,744 · Granted Feb 10, 2026

Inventors: Dae Won Choi (Cheonan-si, KR); Sang Gab Kim (Seoul, KR); Su Bin Bae (Hwaseong-si, KR); Yun Jong Yeo (Hwaseong-si, KR); Da Woon Jung (Hwaseong-si, KR); Yu Gwang Jeong (Anyang-si, KR)

Assignee: SAMSUNG DISPLAY CO., LTD.

H10K59/122H10K50/15H10K50/16H10K71/00H10K59/1201H10K2102/103

Abstract

Claims (41)

1 . A display panel comprising:

a substrate including a plurality of pixel areas;

a via-layer disposed on the substrate;

a plurality of first electrodes disposed on the via-layer and corresponding to the plurality of pixel areas, respectively;

a pixel-defining layer disposed on the via-layer and made of an inorganic insulating material;

first opening parts corresponding to central portions of the first electrodes and penetrating through the pixel-defining layer;

electrode undercuts corresponding to edges of the first opening parts and provided as gaps between the first electrodes and the pixel-defining layer;

a plurality of second opening parts corresponding to peripheries of the first electrodes, respectively, spaced apart from each other, and penetrating through the pixel-defining layer;

via-grooves corresponding to the second opening parts and defined on an upper surface of the via-layer;

via-undercuts provided by the pixel-defining layer around the second opening parts and the via-layer around the via-grooves;

an emitting structure disposed on the first electrodes and the pixel-defining layer; and

a second electrode corresponding to the plurality of pixel areas and disposed on the emitting structure,

wherein the emitting structure disposed on the first electrodes includes an emitting layer, a hole transport layer disposed between the emitting layer and the first electrodes, and an electron transport layer disposed between the emitting layer and the second electrode,

the emitting structure disposed on the pixel defining layer includes the hole transport layer and the electron transport layer, and

the hole transport layer and the electron transport layer of the emitting structure disposed on the pixel defining layer and the second electrode each are partially separated by a corresponding via-undercut.

2 . The display panel of claim 1 , wherein the second opening parts are disposed in non-emitting areas between pixel areas corresponding to different colors and neighboring to each other among the plurality of pixel areas, and are formed in parallel with each other at edges of the first electrodes.

3 . The display panel of claim 2 , wherein each of the via-grooves has a greater width than each of the second opening parts, and

each of the via-undercut is provided by a structure in which a lower surface of the pixel-defining layer around a corresponding second opening part protrudes from the upper surface of the via-layer around a corresponding via-groove.

4 . The display panel of claim 3 , wherein

the emitting layer corresponds to each of the plurality of pixel areas, and

the hole transport layer and the electron transport layer correspond to the plurality of pixel areas.

5 . The display panel of claim 4 , wherein the hole transport layer, the electron transport layer, and the second electrode are further disposed in the via-groove, and

the hole transport layer of the via-groove is separated from the hole transport layer on the pixel-defining layer by the via-undercut.

6 . The display panel of claim 4 , wherein the via-undercut has a width of about 0.35 micrometers (μm) or more.

7 . The display panel of claim 6 , wherein a ratio of a width of the via-undercut to a height of the via-undercut is in a range of about 50 percentages (%) to about 100%.

8 . The display panel of claim 6 , wherein two or more second opening parts are disposed in parallel with each other in the non-emitting areas between two pixel areas corresponding to the different colors and neighboring to each other among the plurality of pixel areas, and

a gap of any two of the two or more second opening parts is about 1 μm or more.

9 . The display panel of claim 4 , further comprising:

a circuit layer disposed on the substrate, including a plurality of thin film transistors corresponding to the plurality of pixel areas, and covered with the via-layer; and

groove protection layers disposed between the circuit layer and the via-layer,

wherein the groove protection layers are disposed in the non-emitting areas between the pixel areas corresponding to the different colors and neighboring to each other among the plurality of pixel areas, and

at least portions of the groove protection layers are exposed to the via-grooves.

10 . The display panel of claim 9 , further comprising an auxiliary via-layer disposed between the circuit layer and the via-layer,

wherein the groove protection layers are disposed on the auxiliary via-layer.

11 . The display panel of claim 10 , wherein the electrode protection layer is made of any one of IZO and IGZO.

12 . The display panel of claim 4 , wherein each of the central portions of the first electrodes corresponding to each of the first opening parts refers to a remaining portion of a corresponding first electrode excluding an edge of the first electrode,

the edge of the first electrode is covered with the pixel-defining layer,

in the electrode undercut, the first electrode and the pixel-defining layer are spaced apart from each other while directly facing each other, and

the emitting structure on the first electrode is separated from the emitting structure on the pixel-defining layer by the electrode undercut.

13 . The display panel of claim 12 , further comprising an electrode protection layer corresponding to an edge of the electrode undercut, disposed on the edge of the first electrode, and covered with the pixel-defining layer,

wherein the electrode undercut is provided by a structure in which the lower surface of the pixel-defining layer corresponding to the edge of the first opening part protrudes from the electrode protection layer.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (20)