Methods and systems of operating a neural circuit in a non-volatile memory based neural-array
View Patent ↗In one aspect, a method of a neuron circuit includes the step of providing a plurality of 2 N −1 single-level-cell (SLC) flash cells for each synapse (Y i ) connected to a bit line forming a neuron. The method includes the step of providing an input vector (X i ) for each synapse Y i wherein each input vector is translated into an equivalent electrical signal ES i (current I DACi , pulse T PULSEi , etc). The method includes the step of providing an input current to each synapse sub-circuit varying from 2 0 *ES i to (2 N −1)*ES i . The method includes the step of providing a set of weight vectors or synapse (Y i ), wherein each weight vector is translated into an equivalent threshold voltage level or resistance level to be stored in one of many non-volatile memory cells assigned to each synapse (Y i ). The method includes the step of providing for 2 N possible threshold voltage levels or resistance levels in the 2 N −1 non-volatile memory cells of each synapse, wherein each cell is configured to store one of the two possible threshold voltage levels. The method includes the step of converting the N digital bits of the weight vector or synapse Y i into equivalent threshold voltage level and store the appropriate cell corresponding to that threshold voltage level in one of the many SLC cells assigned to the weight vector or synapse (Y i ). The method includes the step of turning off all remaining 2 N −1 flash cells of the respective synapse (Y i ). Various other methods are presented of forming neuron circuits by providing a plurality of single-level-cell (SLC) and many-level-cell (MLC) non-volatile memory cells, for each synapse (Y i ) electrically connected to form a neuron. The disclosure shows methods of forming neurons in various configurations for non-volatile memory cells (flash, RRAM etc.); of different storage capabilities per cell—both SLC and MLC cells.
1 . A method of operating neurons using single-level cell (SLC) non-volatile memory cells comprising:
providing a plurality of N single-level-cell (SLC) non-volatile memory cells for each synapse (Yi) connected to a bit line forming a neuron, where N is the number of bits in the weight vector or synapse (Yi);
providing an input vector (Xi) for each synapse (Yi), wherein each input vector (Xi) is translated into an equivalent electrical signal;
providing the electrical signal to each synapse sub-circuit;
providing an input current (IDAci) to each synapse sub-circuit varying from 2{circumflex over ( )}0*IDACi to (2{circumflex over ( )}(N−1))*IDACi, where N is the number of bits in the weight vector or synapse (Yi);
providing a set of weight vectors or synapse (Yi), wherein each weight vector is stored in one of many MSB to LSB SLC non-volatile memory cells assigned for each synapse;
providing for 2N possible threshold voltage levels or resistance levels in the N non-volatile memory cells of each synapse (Yi) with each non-volatile memory cell capable of storing one of the two possible threshold voltage levels or resistance levels; and
storing the N digital bits of the weight vector into equivalent threshold voltage level or resistance level in the corresponding non-volatile memory cell of appropriate significance (MSB to LSB),
wherein the plurality of non-volatile memory cells is ordered from a most significant bit (MSB) to a least significant bit (LSB), N is the number of bits in the weight vector or synapse (Yi); and
wherein the exponential current scaling (2{circumflex over ( )}0*IDACi to (2{circumflex over ( )}(N−1))*IDACi) is combined with the synchronized MSB-to-LSB memory ordering as a unified neural computational architecture.
2 . The method of claim 1 , wherein the step of further comprises:
providing an input pulse (T PULSEi ) to each synapse sub-circuit varying from 2 0 *T PULSEi to (2 N-1 )*T PULSEi .
3 . A method of claim 1 , wherein the non-volatile memory cell is a flash memory cell.