Granted Patent B2

US 12,530,570 · App. 17/882,341 · Granted Jan 20, 2026

Inventor: Vishal Sarin (Santa Clara, CA)

G06N3/063G06F7/49942G06F17/16G06N3/04G06N3/049G06N3/065G06N3/082

Abstract

Claims (13)

1 . A method of operating a neuron circuit in a non-volatile memory-based neural array, the method comprising:

providing a plurality of N many-level-cell (MLC) non-volatile memory cells for each synapse (Yi) connected to a bit line forming a neuron, wherein the plurality of non-volatile memory cells are ordered from a most significant levels (MSLs) to a least significant levels (LSLs), and wherein N is the number of bits in the weight vector of synapse (Yi);

providing an input vector (Xi) for each synapse (Yi), wherein each input vector (Xi) is translated into an equivalent electrical signal ESi;

providing an electrical signal to each synapse sub-circuit, the electrical signal comprising a set of input currents ((2 {circumflex over ( )}{0·k})·IDACi, (2{circumflex over ( )}{1·k})·IDACi, (2{circumflex over ( )}{2·k})·IDACi, . . . ), where k=log 2 (L);

providing a set of weight vectors, wherein each weight vector is translated into an equivalent threshold voltage level or resistance level to be stored in one of many MLC non-volatile memory cells assigned for each synapse;

providing for 2{circumflex over ( )}N possible threshold voltage levels or resistance levels in the (2{circumflex over ( )}N−1)/(L−1) non-volatile memory cells of each synapse, wherein each non-volatile memory cell is configured to store L possible threshold voltage levels or resistance levels, one of which is equivalent to an off state (0 state); and

converting the N digital bits of the weight vector into equivalent threshold voltage level or resistance levels and store the appropriate cell corresponding to that level in one of a plurality of MLC non-volatile memory cells assigned to the weight vector or synapse (Yi).

2 . The method of claim 1 , wherein weight level (W) is stored in sequence from least significant levels non-volatile memory cell to most significant levels non-volatile memory cell in a sequential manner such as if weight level (W) falls within level 0 to L−1, then store W in the least significant levels non-volatile memory cell and turn off the other remaining non-volatile memory cells forming the synapse by storing level 0, which is equivalent to an off cell in the remaining non-volatile memory cells; if weight level (W) falls within level L to 2 (L−1), then store L−1 in the 1st least significant levels non-volatile memory cell, and W-(L−1) in the 2nd least significant levels non-volatile memory cell and turn off the remaining non-volatile memory cells forming the synapse by storing level 0; and to implement the process sequentially for various possible values of weight levels (W) per synapse.

3 . The method of claim 1 , wherein the step of providing an electrical signal to each synapse sub-circuit further comprises:

providing an input current (IDACi) to each synapse sub-circuit.

4 . The method of claim 1 , wherein the step of providing an electrical signal to each synapse sub-circuit further comprises:

providing an input pulse (TPULSEi) to each synapse sub-circuit.

5 . A method of claim 1 , wherein the non-volatile memory cell is a flash memory cell.

Assignments (3)

Continuity (6)

References Cited (9)