METHODS AND SYSTEMS OF OPERATING A NEURAL CIRCUIT IN A NON-VOLATILE MEMORY BASED NEURAL-ARRAY
In one aspect, a method of a neuron circuit includes the step of providing a plurality of 2 N −1 single-level-cell (SLC) flash cells for each synapse (Y i ) connected to a bit line forming a neuron. The method includes the step of providing an input vector (X i ) for each synapse Y i wherein each input vector is translated into an equivalent electrical signal ES i (current I DACi , pulse T PULSEi , etc). The method includes the step of providing an input current to each synapse sub-circuit varying from 2 0 *ES i to (2 N −1)*ES i . The method includes the step of providing a set of weight vectors or synapse (Y i ), wherein each weight vector is translated into an equivalent threshold voltage level or resistance level to be stored in one of many non-volatile memory cells assigned to each synapse (Y i ). The method includes the step of providing for 2 N possible threshold voltage levels or resistance levels in the 2 N −1 non-volatile memory cells of each synapse, wherein each cell is configured to store one of the two possible threshold voltage levels. The method includes the step of converting the N digital bits of the weight vector or synapse Y i into equivalent threshold voltage level and store the appropriate cell corresponding to that threshold voltage level in one of the many SLC cells assigned to the weight vector or synapse (Y i ). The method includes the step of turning off all remaining 2 N −1 flash cells of the respective synapse (Y i ). Various other methods are presented of forming neuron circuits by providing a plurality of single-level-cell (SLC) and many-level-cell (MLC) non-volatile memory cells, for each synapse (Y i ) electrically connected to form a neuron. The disclosure shows methods of forming neurons in various configurations for non-volatile memory cells (flash, RRAM etc.); of different storage capabilities per cell—both SLC and MLC cells.
1 . A method for operating a set of many-level-cell (MLC) non-volatile memory cells in a neuron comprising:
providing a plurality of N/B many level cell (MLC) non-volatile memory cells for each synapse (Y i ) connected to a bit line forming a neuron, wherein the plurality of non-volatile memory cells are ordered from a most significant bits cell (MSB's) to a least significant bits cell (LSB's), and N is the number of bits in the weight vector or synapse (Y i ) and B is the bit storage capacity per non-volatile memory cell;
providing an input vector (X i ) for each synapse (Y i ), wherein each input vector (X i ) is translated into an equivalent electrical signal;
providing an electrical signal to each synapse sub-circuit;
providing a set of weight vectors, wherein each weight vector is stored across many MSB to LSB MLC non-volatile memory cells assigned to each synapse (Y i ); and
storing the N digital bits of the weight vector, such that B bits are stored in each non-volatile memory cell, in order of significance from LSB to MSB.
2 . The method of claim 1 , wherein the step of providing an electrical signal to each synapse sub-circuit further comprises:
providing an input current I DACi to each synapse sub-circuit, from (2 0*k )*I DACi , (2 1*k )*I DACi , (2 2*k )*I DACi , and wherein k=log 2 (L), wherein L is the number of levels possible per non-volatile memory cell.
3 . The method of claim 1 , wherein the step of providing an electrical signal to each synapse sub-circuit further comprises:
providing an input pulse T PULSEi to each synapse sub-circuit, from (2 0*k )*T PULSEi , (2 1*k )*T PULSEi , (2 2*k )*T PULSEi , and wherein k=log 2 (L), wherein L is the number of threshold voltage levels or resistance levels possible per non-volatile memory cell.
4 . The method of claim 1 , wherein the non-volatile memory cell is a flash memory cell.