Granted Patent B2

US 12,224,750 · App. 17/883,874 · Granted Feb 11, 2025

Inventors: Mohammad H. Amin (Coquitlam, CA); Richard G. Harris (North Vancouver, CA)

Assignee: 1372934 B.C. LTD.

H03K19/195G06N10/40

Abstract

Claims (45)

1. A logical qubit comprising:

a first tunable coupler;

a second tunable coupler;

a plurality of fixed couplers comprising at least a first fixed coupler and a second fixed coupler;

a plurality of physical qubits comprising:

a first set of two or more physical qubits connected to the first tunable coupler, at least one of the physical qubits in the first set of two or more physical qubits connected to the first fixed coupler;

a second set of two or more physical qubits connected to the second tunable coupler, at least one of the physical qubits in the second set of two or more physical qubits connected to the second fixed coupler; and

a third set of two or more physical qubits connected between the first fixed coupler and the second fixed coupler; and

wherein:

each of the first tunable coupler, the plurality of fixed couplers, and the second tunable coupler enforce one of even and odd parity in any connected physical qubits of the plurality of physical qubits;

each coupler in the plurality of fixed couplers is connected to at least two physical qubits in the plurality of physical qubits, at least one coupler of the plurality of fixed couplers is in communication with four physical qubits to provide interaction between the four physical qubits;

at least two discrete qubit paths connect the first tunable coupler and the second tunable coupler; and

the first tunable coupler, the second tunable coupler, the plurality of fixed couplers, and the plurality of physical qubits define a lattice.

2. The logical qubit of claim 1 , wherein each of the first tunable coupler and the second tunable coupler are connected to an external qubit, the external qubit comprising an additional physical qubit connected on an outer perimeter of the lattice.

3. The logical qubit of claim 2 , wherein each external qubit is in communication with one or more additional logical qubits.

4. The logical qubit of claim 1 , wherein the plurality of physical qubits comprise pairs of qubits arranged in loops made up of two physical qubits of the plurality of physical qubits, the pairs of qubits coupled by two couplers of the first tunable coupler, the second tunable coupler, and the plurality of fixed couplers.

5. The logical qubit of claim 4 , wherein the plurality of fixed couplers are each respective four qubit parity enforcers, and the first tunable coupler and the second tunable coupler are each respective switchable three qubit parity enforcers.

6. The logical qubit of claim 1 , wherein the plurality of physical qubits comprises twenty four physical qubits arranged in a three-by-three square lattice.

7. The logical qubit of claim 6 , wherein the first and the second tunable couplers are positioned on diagonally opposite corners of the three-by-three square lattice.

8. The logical qubit of claim 6 , wherein the first and the second tunable couplers are positioned on first and second exterior sides of the three-by-three square lattice.

9. The logical qubit of claim 6 , wherein the first and the second tunable couplers are positioned on an interior of the three-by-three square lattice.

10. The logical qubit of claim 1 , further comprising a control signal source coupled to apply a control signal to change a state of one or more physical qubits that make up one of the at least two discrete qubit paths.

11. The logical qubit of claim 10 , wherein the control signal source comprises a microwave line.

12. A quantum processor comprising a plurality of logical qubits, each logical qubit comprising:

a first tunable coupler;

a second tunable coupler;

a plurality of fixed couplers comprising at least a first fixed coupler and a second fixed coupler;

a plurality of physical qubits comprising:

a first set of two or more physical qubits connected to the first tunable coupler, at least one of the physical qubits in the first set of two or more physical qubits connected to the first fixed coupler;

a second set of two or more physical qubits connected to the second tunable coupler, at least one of the physical qubits in the second set of two or more physical qubits connected to the second fixed coupler; and

a third set of two or more physical qubits connected between the first fixed coupler and the second fixed coupler;

wherein:

each of the first tunable coupler, the plurality of fixed couplers, and the second tunable coupler enforce parity in any connected physical qubits;

each coupler in the plurality of fixed couplers is connected to at least two physical qubits in the plurality of physical qubits, at least one coupler of the plurality of fixed couplers is in communication with four physical qubits and providing interaction between the four physical qubits;

wherein at least two discrete qubit paths connect the first tunable coupler and the second tunable coupler;

the first tunable coupler, the second tunable coupler, the plurality of fixed couplers, and the plurality of physical qubits define a lattice; and

each logical qubit of the plurality of logical qubits is communicatively coupled to at least one other logical qubit of the plurality of logical qubits.

13. The quantum processor of claim 12 , wherein coupled logical qubits are connected by two physical qubits and an intermediate coupler.

14. The quantum processor of claim 12 , wherein coupled logical qubits are connected by one shared physical qubit.

15. The quantum processor of claim 12 , wherein coupled logical qubits are directly coupled with a tunable four qubit coupler by sharing a tunable coupler.

16. The quantum processor of claim 12 , wherein multiple logical qubits are coupled by physical qubits connected to an intermediate coupler.

17. The quantum processor of claim 12 , wherein four logical qubits are coupled by four external qubits and an intermediate tunable four qubit coupler, each external qubit comprising an additional physical qubit connected on an outer perimeter of the lattice.

18. The quantum processor of claim 12 , wherein four logical qubits are coupled by a single shared physical qubit.

19. The quantum processor of claim 12 , further comprising a control signal source communicatively coupled to change a state of one or more physical qubits in communication with one of the at least two discrete qubit paths.

20. The quantum processor of claim 19 , wherein the control signal source comprises a microwave line.

Assignments (6)

Continuity (2)

References Cited (349)