Granted Patent B2

US 12,632,760 · App. 17/786,192 · Granted May 19, 2026

Inventors: Reza Molavi (North Vancouver, CA); Mark H. Volkmann (Burnaby, CA); Emile M. Hoskinson (Vancouver, CA); Richard G. Harris (North Vancouver, CA); Trevor M. Lanting (Vancouver, CA); Paul I. Bunyk (Pt. Roberts, WA); Andrew J. Berkley (Vancouver, CA)

Assignee: D-WAVE SYSTEMS INC.

G06N10/40H10N60/12G06F30/347G06F30/392G06F30/394

Abstract

Claims (35)

1 . An analog computing system comprising a qubit, the qubit comprising:

a Josephson junction;

a first qubit loop formed by a first superconducting current path; and

a second qubit loop formed by a second superconducting current path;

wherein the first qubit loop and the second qubit loop are electrically connected in parallel across the Josephson junction, and a position of the Josephson junction along the first qubit loop defines a critical distance dividing the first qubit loop into a near inductor regime and a far inductor regime where adding a lumped inductance in the near inductor regime decreases a qubit capacitance at the Josephson junction and where adding the lumped inductance in the far inductor regime increases the qubit capacitance at the Josephson junction, the analog computing system further comprising:

a plurality of inductors disposed along the first qubit loop, each of the plurality of inductors tunable to provide a tunable inductance, the plurality of inductors comprising:

one or more near inductors, each near inductor disposed in the near inductor regime; and

one or more far inductors, each far inductor disposed in the far inductor regime.

2 . The analog computing system according to claim 1 further comprising one or more couplers tunably coupleable to the first qubit loop, each of the one or more couplers tunable to provide a respective coupling strength with the qubit.

3 . The analog computing system according to claim 2 wherein the tunable inductance for each of the plurality of inductors is tunable within a corresponding inductance range and each of the one or more couplers has a corresponding coupler-induced inductance range, each coupler-induced inductance range comprising a difference in a qubit inductance at the Josephson junction between states of the corresponding one of the one or more couplers, and a sum of the tunable inductance ranges of the plurality of inductors is greater than each of the corresponding coupler-induced inductance ranges.

4 . The analog computing system according to claim 3 wherein the sum of the tunable inductance ranges of the plurality of inductors is greater than a total coupler-induced inductance range, the total coupler-induced inductance range comprising a difference between a first coupler-induced inductance and a second coupler-induced inductance, the first coupler-induced inductance comprising the qubit inductance in a first state where each of the one or more couplers is ferromagnetically coupled to the qubit and the second coupler-induced inductance comprising the qubit inductance in a second state where each of the one or more couplers is anti-ferromagnetically coupled to the qubit.

5 . The analog computing system according to claim 4 wherein:

the one or more near inductors collectively are tunable to reduce the qubit capacitance from a first coupler-induced capacitance to within a first threshold of a target capacitance;

the one or more far inductors collectively are tunable to increase the qubit capacitance from a second coupler-induced capacitance to within a second threshold of the target capacitance;

the first coupler-induced capacitance comprises the qubit capacitance in a third state where each of the one or more couplers that is in the near inductor regime is anti-ferromagnetically coupled to the first qubit loop and each of the one or more couplers that is in the far inductor regime is ferromagnetically coupled to the first qubit loop; and

the second coupler-induced capacitance comprises the qubit capacitance in a fourth state where each of the one or more couplers that is in the near inductor regime is ferromagnetically coupled to the first qubit loop and each of the one or more couplers that is in the far inductor regime is anti-ferromagnetically coupled to the first qubit loop.

6 . The analog computing system according to claim 5 wherein, for a predetermined target qubit inductance and a predetermined set of coupling strengths for the one or more couplers, the plurality of inductors are tunable to provide a total tunable inductance for each of the first, second, third, and fourth states which increases the qubit inductance to within a third threshold of the predetermined target qubit inductance and at least one of: increases and reduces the qubit capacitance to within a fourth threshold of the target capacitance.

7 . The analog computing system according to claim 2 wherein one inductor of the plurality of inductors comprises one or more inductor Josephson junctions interrupting the first qubit loop and tunable to provide a respective tunable inductance range of the one inductor of the plurality of inductors.

8 . The analog computing system according to claim 7 wherein the one of the plurality of inductors comprises one or more DC-SQUIDs, the one or more DC-SQUIDs comprising the one or more inductor Josephson junctions.

9 . The analog computing system according to claim 8 wherein the one of the plurality of inductors comprises a plurality of DC-SQUIDs connected in series along the first qubit loop.

10 . The analog computing system according to claim 1 wherein the qubit comprises at least one secondary inductor disposed along the second qubit loop.

11 . The analog computing system according to claim 10 wherein the first qubit loop and the second qubit loop partially overlap along a shared portion and a shared inductor of the plurality of inductors is disposed along the shared portion.

12 . The analog computing system according to claim 11 wherein the shared inductor comprises one of the one or more near inductors.

13 . The analog computing system according to claim 10 wherein the at least one secondary inductor comprises:

one or more secondary near inductors, each secondary near inductor disposed along the second qubit loop less than a second critical distance from the Josephson junction; and

one or more secondary far inductors, each secondary far inductor disposed along the second qubit loop more than the second critical distance from the Josephson junction.

14 . The analog computing system according to claim 13 wherein the plurality of inductors and the at least one secondary inductor collectively provide a collective tunable inductance range of at least twice a total coupler-induced inductance range.

15 . The analog computing system of claim 1 , further comprising a first flux bias line in communication with the first qubit loop and a second flux bias line in communication with the second qubit loop, the first flux bias line receiving signals independently from the second flux bias line.

16 . The analog computing system of claim 1 , wherein the second qubit loop comprises a first portion in communication with the Josephson junction and a second portion spaced from the Josephson junction, the first portion and the second portion being separated by a crossing, wherein a current in the second qubit loop travels in a first rotational direction in the first portion and a second rotational direction that is opposite to the first rotational direction in the second portion.

17 . The analog computing system of claim 1 , wherein the Josephson junction comprises one of a compound Josephson junction or a compound-compound Josephson junction.

18 . The analog computing system of claim 1 , wherein the first qubit loop and the second qubit loop partially overlap along a shared portion.

19 . The analog computing system of claim 1 , further comprising a coupler tunably coupled to one of the first qubit loop and the second qubit loop.

20 . The analog computing system of claim 19 , further comprising a second qubit coupled to the coupler.

21 . The analog computing system of claim 1 , wherein the first qubit loop and the second qubit loop are symmetric about an axis of the Josephson junction, the axis of the Josephson junction intersecting a first connection between the first qubit loop and the second qubit loop and the Josephson junction and a second connection between the first qubit loop and the second qubit loop and the Josephson junction.

22 . The analog computing system of claim 1 , further comprising one or more additional qubit loops electrically connected in parallel across the Josephson junction.

Assignments (6)

Continuity (2)

References Cited (400)