Wafer-on-wafer formed memory and logic
A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.
1 . An apparatus, comprising:
a memory device formed on a memory die, the memory device comprising:
an array of memory cells; and
memory-to-logic circuitry coupled to the array of memory cells;
a logic device formed on a logic die, the logic device comprising:
logic circuitry; and
logic-to-memory circuitry coupled to the logic circuitry; and
a bond formed between the memory die and the logic die via a wafer-on-wafer bonding process;
wherein the memory-to-logic circuitry is configured to transmit signals indicative of data between the array of memory cells and the logic-to-memory circuitry via the bond;
wherein the logic-to-memory circuitry is configured to transmit signals indicative of data between the logic circuitry and the memory-to-logic circuitry via the bond; and
wherein the logic circuitry comprises one of:
an artificial intelligence accelerator;
a communication circuit from a group of communication circuits including a radio frequency communication circuit and a 5G communication circuit;
a sensor circuit from a group of sensor circuits including a video circuit, an imaging circuit, a radar circuit, and a smart sensor circuit; and
a network circuit from a group of network circuits including a packet routing circuit and an intrusion-detection circuit.
2 . The apparatus of claim 1 , wherein the bond is formed via the wafer-on-wafer bonding process between a first wafer including the memory device formed on the memory die and a second wafer including the logic device formed on the logic die; and
wherein the apparatus is singulated from the bonded first and second wafers.
3 . The apparatus of claim 1 , wherein the memory device further comprises:
a host interface coupled to the array of memory cells; and
a transceiver coupled to the host interface and to the memory-to-logic circuitry;
wherein the transceiver is configured to select a data output path for the memory array between the host interface and the memory-to-logic circuitry.
4 . The apparatus of claim 1 , wherein the memory device further comprises a host interface coupled to the array of memory cells;
wherein the logic device further comprises a transceiver coupled to the logic-to-memory circuitry and to the logic circuitry; and
wherein the transceiver is configured to select a data output path for the memory array between the host interface and the memory-to-logic circuitry.