IP Library › Granted Patent US 12,618,880
Granted Patent B2
US 12,618,880 · App. 17/884,753 · Granted May 5, 2026

Ultra-low-power front end for beyond-the-rails voltage sensing

Inventors: Arashk Norouzpourshirazi (Austin, TX); Stephen T. Hodapp (Austin, TX); Ravi K. Kummaraguntla (Austin, TX); Axel Thomsen (Austin, TX)
Assignee: Cirrus Logic Inc.
G01R19/2506
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Quick Facts
Patent No.
US 12,618,880
App. No.
17/884,753
Granted
May 5, 2026
Kind
B2
Abstract

A system may include a passive floating attenuator configured to receive an analog physical quantity and attenuate the analog physical quantity to a floating attenuated signal defined by voltage nodes other than the voltage nodes of the analog physical quantity, an anti-aliasing filter configured to filter the floating attenuated signal to generate a filtered attenuated signal, and a switched-capacitor sampling circuit comprising a plurality of switches configured to sample the filtered attenuated signal.

Claims (24)

1 . A system comprising:

a passive floating attenuator configured to receive an analog physical quantity and attenuate the analog physical quantity to a floating attenuated signal defined by voltage nodes other than the voltage nodes of the analog physical quantity;

an anti-aliasing filter configured to filter the floating attenuated signal to generate a filtered attenuated signal; and

a switched-capacitor sampling circuit comprising a plurality of switches configured to sample the filtered attenuated signal.

2 . The system of claim 1 , wherein the passive floating attenuator comprises a resistive divider.

3 . The system of claim 1 , wherein the switched-capacitor sampling circuit comprises a common-mode insensitive sampling circuit insensitive to a common mode of the filtered attenuated signal.

4 . The system of claim 1 , further comprising a bootstrap generation network electrically coupled to the plurality of switches and configured to:

generate a bootstrap sampling clock for controlling the plurality of switches; and

generate a floating supply voltage for the bootstrap sampling clock based on the filtered attenuated signal.

5 . The system of claim 4 , further comprising a unity gain buffer configured to buffer the filtered attenuated signal used for generating the bootstrap sampling clock in order to isolate an output of the anti-aliasing filter from the bootstrap generation network.

6 . The system of claim 5 wherein the unity gain buffer is powered from a floating supply that is derived from and tracks a highest-voltage beyond-the-rails component of the analog physical quantity.

7 . The system of claim 1 , wherein the analog physical quantity is a voltage.

8 . A method comprising:

attenuating, with a passive floating attenuator, an analog physical quantity to a floating attenuated signal defined by voltage nodes other than the voltage nodes of the analog physical quantity;

filtering, with an anti-aliasing filter, the floating attenuated signal to generate a filtered attenuated signal; and

sampling the filtered attenuated signal with a switched-capacitor sampling circuit comprising a plurality of switches.

9 . The method of claim 8 , wherein the passive floating attenuator comprises a resistive divider.

10 . The method of claim 8 , wherein the switched-capacitor sampling circuit comprises a common-mode insensitive sampling circuit insensitive to a common mode of the filtered attenuated signal.

11 . The method of claim 8 , further comprising:

generating, with a bootstrap generation network electrically coupled to the plurality of switches, a bootstrap sampling clock for controlling the plurality of switches; and

generating, with the bootstrap generation network, a floating supply voltage for the bootstrap sampling clock based on the filtered attenuated signal.

12 . The method of claim 11 , further comprising buffering, with a unity gain buffer, the filtered attenuated signal used for generating the bootstrap sampling clock in order to isolate an output of the anti-aliasing filter from the bootstrap generation network.

13 . The method of claim 12 , wherein the unity gain buffer is powered from a floating supply that is derived from and tracks a highest-voltage beyond-the-rails component of the analog physical quantity.

14 . The method of claim 8 , wherein the analog physical quantity is a voltage.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2026
From: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
To: CIRRUS LOGIC, INC.
Reel/Frame 074045/0078 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2022
From: NOROUZPOURSHIRAZI, ARASHK; HODAPP, STEPHEN T.; KUMMARAGUNTLA, RAVI K.; THOMSEN, AXEL
To: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
Reel/Frame 060875/0347 →
Continuity (1)
Related Publication 20240053387A1 · Feb 15, 2024
References Cited (8)
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