CONCURRENT COMPUTE CONTEXT
Embodiments described herein provide a system of concurrent compute queues that enable the scheduling of a large number of compute contexts simultaneously on graphics processor hardware. One embodiment provides an apparatus comprising a system interface and a general-purpose graphics processor coupled with the system interface. The general-purpose graphics processor comprises a plurality of graphics processor hardware resources configured to be partitioned into a plurality of isolated partitions, each of the plurality of isolated partitions including a first command streamer, a second command streamer, and circuitry configured to schedule general-purpose graphics compute workloads submitted to a first plurality of command queues associated with the first command streamer and a second plurality of command queues associated with the second command streamer.
1 . An apparatus comprising:
a system interface; and
a general-purpose graphics processor coupled with the system interface, the general-purpose graphics processor comprising:
a plurality of graphics processor hardware resources configured to be partitioned into a plurality of isolated partitions, each of the plurality of isolated partitions including:
a first command streamer;
a second command streamer; and
circuitry configured to schedule general-purpose graphics compute workloads submitted to a first plurality of command queues associated with the first command streamer and a second plurality of command queues associated with the second command streamer.
2 . The apparatus as in claim 1 , wherein each of the plurality of isolated partitions includes a cluster of graphics processor cores.
3 . The apparatus as in claim 1 , wherein each of the plurality of isolated partitions includes a tile of graphics processor engines.
4 . The apparatus as in claim 3 , wherein each of the plurality of isolated partitions resides on a separate semiconductor die.
5 . The apparatus as in claim 1 , wherein the plurality of isolated partitions include a first isolated partition and a second isolated partition, wherein the first isolated partition and the second isolated partition include separate functional units, separate cache memory, and separate paths to local memory of the general-purpose graphics processor.
6 . The apparatus as in claim 5 , wherein the first isolated partition is presented via the system interface as a first sub-device and the second isolated partition is presented via the system interface as a second sub-device.
7 . The apparatus as in claim 6 , wherein the first isolated partition includes a first compute partition and a second compute partition, the first compute partition and the second compute partition configurable to execute separate compute contexts while sharing graphics processor hardware resources of the first isolated partition.
8 . The apparatus as in claim 7 , wherein the first command streamer of the first isolated partition is associated with the first compute partition and the second command streamer of the first isolated partition is associated with the second isolated partition.
9 . A method comprising:
selecting a first command queue for scheduling at a first isolated partition of a graphics processor device, wherein the first command queue is one of a plurality of command queues of the first isolated partition;
acquiring at least a minimum number of graphics processor hardware resources of the first isolated partition to associate with the first command queue, wherein the first command queue includes commands associated with a workload and the workload specifies the minimum number of graphics processor hardware resources;
dispatching threads of the workload to physical thread slots of at least the minimum number of graphics processor hardware resources; and
load balancing a number of graphics processor hardware resources assigned to the workload between the minimum number of graphics processor hardware resources and a maximum number of graphics processor hardware resources.
10 . The method as in claim 9 , further comprising determining the maximum number of graphics processor hardware resources based on an attribute of a command buffer that stores commands of the workload.
11 . The method as in claim 10 , wherein the minimum number of graphics processor hardware resources and the maximum number of graphics processor hardware resources is specified as a percentage of total graphics processor hardware resources of the first isolated partition.
12 . The method as in claim 11 , further comprising converting the minimum number of graphics processor hardware resources and the maximum number of graphics processor hardware resources from the percentage of total graphics processor hardware resources of the first isolated partition to a number of graphics processor hardware resources of the first isolated partition.
13 . The method as in claim 9 , further comprising:
selecting a second command queue for scheduling at a second isolated partition of the graphics processor device; and
dispatching threads of a workload associated with the second command queue concurrently with dispatching threads of the workload associated with the first command queue.
14 . A graphics processing system comprising:
a system interface;
a memory device; and
a general-purpose graphics processor coupled with the system interface and the memory device, the general-purpose graphics processor comprising:
a plurality of graphics processor hardware resources configured to be partitioned into a plurality of isolated partitions, each of the plurality of isolated partitions including:
a first command streamer;
a second command streamer; and
circuitry configured to schedule general-purpose graphics compute workloads submitted to a first plurality of command queues associated with the first command streamer and a second plurality of command queues associated with the second command streamer.
15 . The graphics processing system as in claim 14 , wherein each of the plurality of isolated partitions includes a cluster of graphics processor cores or a tile of graphics processor engines.
16 . The graphics processing system as in claim 15 , wherein each of the plurality of isolated partitions resides on a separate semiconductor die.
17 . The graphics processing system as in claim 14 , wherein the plurality of isolated partitions include a first isolated partition and a second isolated partition, wherein the first isolated partition and the second isolated partition include separate functional units, separate cache memory, and separate paths to local memory of the general-purpose graphics processor.
18 . The graphics processing system as in claim 17 , wherein the first isolated partition is presented via the system interface as a first sub-device and the second isolated partition is presented via the system interface as a second sub-device.
19 . The graphics processing system as in claim 18 , wherein the first isolated partition includes a first compute partition and a second compute partition, the first compute partition and the second compute partition configurable to execute separate compute contexts while sharing graphics processor hardware resources of the first isolated partition.
20 . The graphics processing system as in claim 19 , wherein the first command streamer of the first isolated partition is associated with the first compute partition and the second command streamer of the first isolated partition is associated with the second isolated partition.