Semiconductor device and electronic device
View Patent ↗A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The currents output from the first and second circuits to the first wiring or the second wiring are determined in accordance with the first and second potentials held at the first and second holding nodes.
1. A semiconductor device comprising a first circuit and a second circuit,
the first circuit comprises:
first to fourth transistors; and
a first capacitor,
the second circuit comprises:
fifth to eighth transistors; and
a second capacitor,
wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,
wherein a first terminal of the second transistor is electrically connected to a first terminal of the third transistor and a first terminal of the fourth transistor,
wherein the first terminal of the third transistor is electrically connected to the first terminal of the fourth transistor,
wherein a second terminal of the third transistor is electrically connected to a first wiring,
wherein a gate of the third transistor is electrically connected to a first input wiring,
wherein a second terminal of the fourth transistor is electrically connected to a second wiring, and
wherein a gate of the fourth transistor is electrically connected to a second input wiring.
2. An electronic device comprising the semiconductor device according to claim 1 , configured to perform arithmetic operation of a neural network using the semiconductor device.
3. A semiconductor device comprising a first circuit and a second circuit,
the first circuit comprises:
first to fourth transistors; and
a first capacitor,
the second circuit comprises:
fifth to eighth transistors; and
a second capacitor,
wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor and a first terminal of the first capacitor,
wherein a first terminal of the second transistor is electrically connected to a second terminal of the first capacitor,
wherein a second terminal of the second transistor is electrically connected to a first terminal of the third transistor and a second terminal of the fourth transistor,
wherein the first terminal of the third transistor is electrically connected to the first terminal of the fourth transistor,
wherein a second terminal of the third transistor is electrically connected to a first wiring,
wherein a gate of the third transistor is electrically connected to a first input wiring,
wherein a second terminal of the fourth transistor is electrically connected to a second wiring, and
wherein a gate of the fourth transistor is electrically connected to a second input wiring.
4. An electronic device comprising the semiconductor device according to claim 3 , configured to perform arithmetic operation of a neural network using the semiconductor device.
5. A semiconductor device comprising a first circuit and a second circuit,
the first circuit comprises:
first to fourth transistors; and
a first capacitor,
the second circuit comprises:
fifth to eighth transistors; and
a second capacitor,
wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,
wherein a first terminal of the second transistor is electrically connected to a first terminal of the third transistor and a first terminal of the fourth transistor,
wherein the first terminal of the third transistor is electrically connected to a first terminal of the fourth transistor,
wherein a second terminal of the third transistor is electrically connected to a first wiring,
wherein a gate of the third transistor is electrically connected to a first input wiring,
wherein a second terminal of the fourth transistor is electrically connected to a second wiring,
wherein a gate of the fourth transistor is electrically connected to a second input wiring,
wherein a first terminal of the fifth transistor is electrically connected to a gate of the sixth transistor,
wherein a first terminal of the sixth transistor is electrically connected to a first terminal of the seventh transistor and a first terminal of the eighth transistor,
wherein the first terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor,
wherein a second terminal of the seventh transistor is electrically connected to the second wiring,
wherein a gate of the seventh transistor is electrically connected to the first input wiring,
wherein a second terminal of the eighth transistor is electrically connected to the first wiring, and
wherein a gate of the eighth transistor is electrically connected to the second input wiring.
6. An electronic device comprising the semiconductor device according to claim 5 , configured to perform arithmetic operation of a neural network using the semiconductor device.