Wafer-on-wafer formed memory and logic for genomic annotations
A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of a genetic sequence from the memory die and through a wafer-on-wafer bond. The logic die can also perform a genome annotation lotic operation to attach biological information to the genetic sequence. An annotated genetic sequence can be provided as an output.
1. A method comprising:
receiving, at a logic die that is bonded to a memory die via a wafer-on-wafter bonding process, signals indicative of a genetic sequence from the memory die and through a wafer-on-wafter bond;
performing, at the logic die, a genome annotation logic operation to attach biological information to the genetic sequence; and
providing an annotated genetic sequence as an output.
2. The method of claim 1 , wherein providing the annotated genetic sequence comprises transmitting signals indicative of the annotated genetic sequence to a host via an output other than the wafer-on-wafer bond.
3. The method of claim 1 , wherein the biological information attached to the genetic sequence includes introns, exons, intron-exon boundaries, regulatory sequences, repeats, gene names, open reading frames, untranslated regions, and protein products.
4. The method of claim 3 , further comprising predicting the protein products based on a given environmental condition.
5. The method of claim 1 , further comprising differentiating multiple genes with an overlapping reading frame.
6. The method of claim 1 , further comprising comparing the annotated genome sequence to a previously completed known annotated genome.
7. The method of claim 1 , further comprising:
generating a visual representation of the annotated genetic sequence; and
providing the visual representation of the annotated genetic sequence to a user via a user interface.
8. A method comprising:
receiving, at a logic die that is bonded to a memory die via a wafer-on-wafter bonding process, signals indicative of input data from the memory die and through a wafer-on-wafter bond; and
accelerating large processing bandwidth logical operations performed by a host via logic circuitry of the logic die by:
performing large data volume logic operations on the input data; and
transmitting processed input data to the memory die via the wafer-on-wafer bond for exchange with the host via an input/output other than the wafer-on-wafer bond;
wherein the large processing bandwidth logical operations are large relative to a processing capability of the logic circuitry of the logic die; and
wherein the large data bandwidth logical operations are large relative to a data input/output capability of one or more processors of the host.
9. The method of claim 8 , wherein receiving the input data comprises receiving the input data through the wafer-on-wafer bond from a plurality of local input/output lines of the memory die.
10. The method of claim 8 , wherein the large processing bandwidth logical operations comprise fluid dynamic analysis operations.
11. The method of claim 8 , wherein the large processing bandwidth logical operations comprise graph analysis operations; and
wherein the large data bandwidth operations comprise node relationship operations.
12. The method of claim 8 , wherein the large processing bandwidth logical operations comprise image processing operations; and
wherein the large data bandwidth logical operations comprise image shading operations.
13. The method of claim 8 , wherein the large processing bandwidth logical operations comprise natural language processing operations.
14. The method of claim 8 , wherein the large data bandwidth logical operations comprise blockchain operations.
15. The method of claim 8 , wherein the large data bandwidth logical operations comprise facial recognition operations.
16. The method of claim 8 , wherein the large data bandwidth logical operations comprise augmented reality operations.
17. The method of claim 8 , wherein the large data bandwidth logical operations comprise network traffic intrusion detection operations.
18. An apparatus, comprising:
a memory die, comprising:
a memory array;
a plurality of local input/output lines (LIOs) coupled to the memory array; and
a global input/output line coupled to the plurality of LIOs and to a host interface;
a logic die bonded to the memory die via a wafer-on-wafer bonding process, the logic die comprising logic circuitry configured to:
receive signals indicative of data from the memory die and through a wafer-on-wafter bond to the plurality of LIOs, wherein the data comprises genetic sequence data;
perform genome annotation logic operations to attach biological information to the genetic sequence data; and
generate an annotated genetic sequence based on the genome annotation logic operations.
19. The apparatus of claim 18 , wherein the logic circuitry is configured to perform the genome annotation logic operation on an amount of data that is greater than an amount of data transferred across the host interface as part of a single host memory access request.
20. The apparatus of claim 18 , wherein the genetic sequence is a deoxyribonucleic acid (DNA) sequence or a ribonucleic acid (RNA) sequence.