Integrating analog-to-digital converter and semiconductor device
An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.
1. An integrating analog-to-digital converter comprising:
a global counter outputting a counter code signal including a multiphase signal;
a column circuit including:
a ramp wave generation circuit outputting a ramp wave voltage whose voltage value changes linearly according to time change;
a comparator comparing the ramp wave voltage with a pixel voltage generated by a pixel; and
a latch circuit latching the counter code signal at timing at which an output of the comparator is inverted;
an output value of the latch circuit being converted into a digital conversion output value per the column circuit; and
a phase division circuit inputting the counter code signal, generating a phase division signal that divides a phase of the counter code signal, and outputting the phase division signal to the latch circuit as an LSB of the digital conversion output value of the integrating analog-to-digital converter,
wherein the global counter is shared to a predetermined number of the column circuit, and
wherein the phase division circuit is arranged for a plurality of column circuits composed of the column circuit, the number of column circuits being a number smaller than the predetermined number, and the LSB is shared by a plurality of phase division circuits composed of the phase division circuit.
2. The integrating analog-to-digital converter according to claim 1 ,
wherein the phase division circuit is arranged per one to several hundred column circuits from the global counter.
3. The integrating analog-to-digital converter according to claim 1 ,
wherein the phase division circuit is arranged in a column circuit that operates at a speed higher than operating frequencies of adjacent column circuits, or is arranged within one to several hundred column circuits from the column circuit.
4. The integrating analog-to-digital converter according to claim 1 ,
wherein the phase division signal is configured to input a plurality of counter code signals composed of the counter code signal and represent the LSB by single or more of a plurality of phase division signals composed of the phase division signal.
5. The integrating analog-to-digital converter according to claim 1 ,
wherein the phase division signal is configured to input a plurality of counter code signals composed of the counter code signal and change a phase of the phase division signal at an arbitrary position between phase change points of the plurality of counter code signals.
6. The integrating analog-to-digital converter according to claim 1 ,
wherein a counter code signal inputted to the phase division circuit is a Johnson counter code signal, counter code signals adjacent to each other are different from each other in ⅛ cycle phase and each have a duty of 50%, and four Johnson counter codes, which are different from one another in ⅛ cycle phase, are inputted in the phase division circuit in parallel.
7. The integrating analog-to-digital converter according to claim 1 ,
wherein a counter code signal, which is not inputted in the phase division circuit and corresponds to an output value of the latch circuit to be a high-order bit of the digital conversion output value of the integrating analog-to-digital converter, is a gray code signal.
8. A semiconductor device comprising:
the integrating analog-to-digital converter according to claim 1 ; and
a semiconductor circuit.
9. A semiconductor device including a column circuit driven by a counter code signal, which is generated by a clock generator, being transmitted across the column circuit in a previous stage, a plurality of column circuits composed of the column circuit being connected in parallel, the semiconductor device comprising:
a phase division circuit generating a phase division circuit whose phase is changed at an arbitrary position between phase change points of the counter code signal when the counter code signal is a multiphase counter code signal,
wherein the phase division circuit is arranged in the column circuit, which uses a frequency higher than a frequency of the counter code signal, or arranged within a range of one to several hundred column circuits from the column circuit.