Integrated assemblies

1. An integrated assembly, comprising:

a memory array over a base;

vertically-extending digit lines associated with the memory array;

sense amplifiers comprising first sense-amplifier-circuitry under the memory array and coupled with the digit lines, circuitry of the first sense-amplifier-circuitry configured to be utilized to provide signal boost during READ/WRITE operations; and

routing structures coupled to each of the digit lines and extending to Mux components; the Mux components being in one-to-one correspondence with the digit lines; each of the Mux components comprising a first transistor and a second transistor; the first transistors having first gates, first source/drain regions and second source/drain regions; the first gates gatedly coupling the first and second source/drain regions with one another; the second transistors having second gates, third source/drain regions and fourth source/drain regions; the second gates gatedly coupling the third and fourth source/drain regions with one another; the routing structures being coupled with the second and third source/drain regions; the first source/drain regions being coupled with second sense-amplifier-circuitry comprising a different type of sense-amplifier-circuitry compared to the first sense-amplifier-circuitry; the fourth source/drain regions being coupled with a voltage source; the first and second gates being coupled with Mux-Driver-circuitry configured to selectively activate/deactivate the first and second gates.

2. The integrated assembly of claim 1 wherein the Mux-Driver-circuitry is associated with the base and is laterally offset from the second sense-amplifier-circuitry.

3. The integrated assembly of claim 1 wherein the first transistors have higher threshold voltages than the second transistors.

4. The integrated assembly of claim 1 wherein the first transistors have substantially the same threshold voltage as the second transistors.

5. The integrated assembly of claim 1 wherein:

the first sense amplifier-circuitry is in configurations having no more than 4 transistors; and

the second sense amplifier-circuitry is in configurations having at least 8 transistors.

6. The integrated assembly of claim 5 wherein the second sense amplifiers are in configurations having at least 12 transistors.

7. The integrated assembly of claim 1 wherein:

the first sense-amplifier-circuitry comprises a first threshold voltage associated therewith;

the second sense-amplifier-circuitry comprises a second threshold voltage associated therewith; and

the second threshold voltage is greater than the first threshold voltage.

8. The integrated assembly of claim 1 wherein the sense amplifiers are local sense amplifiers, wherein the second sense-amplifier-circuitry comprises global sense amplifiers, and wherein at least 10 of the local sense amplifiers are associated with each of the global sense amplifiers.

9. The integrated assembly of claim 1 wherein the sense amplifiers are local sense amplifiers, wherein the second sense-amplifier-circuitry comprises global sense amplifiers, and wherein at least 100 of the local sense amplifiers are associated with each of the global sense amplifiers.

10. The integrated assembly of claim 1 wherein the sense amplifiers are local sense amplifiers, wherein the second sense-amplifier-circuitry comprises global sense amplifiers, and wherein at least 500 of the local sense amplifiers are associated with each of the global sense amplifiers.

11. The integrated assembly of claim 1 further comprising an equalizer utilized to equilibrate the sense amplifiers.

12. The integrated assembly of claim 11 further comprising a pair of transistors utilized to equilibrate the sense amplifiers.

13. The integrated assembly of claim 12 wherein the equalizer is configured for controlling activation/deactivation of the pair of transistors.

14. The integrated assembly of claim 11 wherein voltages from the digit lines are utilized to equilibrate the sense amplifiers.

15. The integrated assembly of claim 1 wherein the circuitry of the first sense-amplifier-circuitry is configured to be utilized to additionally provide for PRECHARGE operations.

16. The integrated assembly of claim 1 wherein the circuitry of the first sense-amplifier-circuitry is configured to be utilized to additionally provide for REFRESH operations.

17. The integrated assembly of claim 1 wherein circuitry of the second sense-amplifier-circuitry is configured to be utilized to provide only READ/WRITE operations.

18. The integrated assembly of claim 1 wherein the circuitry of the first sense-amplifier-circuitry is configured to be utilized to additionally provide for:

REFRESH operations; and

PRECHARGE operations.

19. An integrated assembly, comprising:

a memory array over a base;

vertically-extending digit lines associated with the memory array;

sense amplifiers under the memory array and coupled with the digit lines, wherein circuitry of at least one sense amplifier is configured to be utilized to provide for REFRESH operations and PRECHARGE operations;

routing structures coupled to each of the digit lines and extending to Mux components; the Mux components being in one-to-one correspondence with the digit lines; each of the Mux components comprising a first transistor and a second transistor; the first transistors having first gates, first source/drain regions and second source/drain regions; the first gates gatedly coupling the first and second source/drain regions with one another; the second transistors having second gates, third source/drain regions and fourth source/drain regions; the second gates gatedly coupling the third and fourth source/drain regions with one another; the routing structures being coupled with the second and third source/drain regions; the first source/drain regions being coupled with second sense-amplifier-circuitry; the fourth source/drain regions being coupled with a voltage source; the first and second gates being coupled with Mux-Driver-circuitry configured to selectively activate/deactivate the first and second gates; and

wherein the Mux-Driver-circuitry is associated with the base and is laterally offset from the second sense-amplifier-circuitry.

20. An integrated assembly, comprising:

a memory array over a base;

vertically-extending digit lines associated with the memory array;

sense amplifiers under the memory array and coupled with the digit lines;

routing structures coupled to each of the digit lines and extending to Mux components; the Mux components being in one-to-one correspondence with the digit lines; each of the Mux components comprising a first transistor and a second transistor; the first transistors having first gates, first source/drain regions and second source/drain regions; the first gates gatedly coupling the first and second source/drain regions with one another; the second transistors having second gates, third source/drain regions and fourth source/drain regions; the second gates gatedly coupling the third and fourth source/drain regions with one another; the routing structures being coupled with the second and third source/drain regions; the first source/drain regions being coupled with second sense-amplifier-circuitry; the fourth source/drain regions being coupled with a voltage source; the first and second gates being coupled with Mux-Driver-circuitry configured to selectively activate/deactivate the first and second gates; and

wherein the first transistors have higher threshold voltages than the second transistors.

21. An integrated assembly, comprising:

a memory array over a base;

vertically-extending digit lines associated with the memory array;

sense amplifiers under the memory array and coupled with the digit lines, wherein circuitry of at least one sense amplifier is configured to be utilized to provide for PRECHARGE operations and signal boosting operations;

routing structures coupled to each of the digit lines and extending to Mux components; the Mux components being in one-to-one correspondence with the digit lines; each of the Mux components comprising a first transistor and a second transistor; the first transistors having first gates, first source/drain regions and second source/drain regions; the first gates gatedly coupling the first and second source/drain regions with one another; the second transistors having second gates, third source/drain regions and fourth source/drain regions; the second gates gatedly coupling the third and fourth source/drain regions with one another; the routing structures being coupled with the second and third source/drain regions; the first source/drain regions being coupled with second sense-amplifier-circuitry; the fourth source/drain regions being coupled with a voltage source; the first and second gates being coupled with Mux-Driver-circuitry configured to selectively activate/deactivate the first and second gates; and

wherein the first transistors have substantially the same threshold voltage as the second transistors.

22. An integrated assembly, comprising:

a memory array over a base;

vertically-extending digit lines associated with the memory array;

sense amplifiers under the memory array and coupled with the digit lines;

routing structures coupled to each of the digit lines and extending to Mux components; the Mux components being in one-to-one correspondence with the digit lines; each of the Mux components comprising a first transistor and a second transistor; the first transistors having first gates, first source/drain regions and second source/drain regions; the first gates gatedly coupling the first and second source/drain regions with one another; the second transistors having second gates, third source/drain regions and fourth source/drain regions; the second gates gatedly coupling the third and fourth source/drain regions with one another; the routing structures being coupled with the second and third source/drain regions; the first source/drain regions being coupled with second sense-amplifier-circuitry; the fourth source/drain regions being coupled with a voltage source; the first and second gates being coupled with Mux-Driver-circuitry configured to selectively activate/deactivate the first and second gates; and

wherein:

the sense amplifiers are first sense amplifiers;

the second sense-amplifier-circuitry comprises second sense amplifiers;

the first sense amplifiers are in configurations having no more 4 transistors; and

the second sense amplifiers are in configurations having at least 8 transistors.

23. The integrated assembly of claim 22 wherein the second sense amplifiers are in configurations having at least 12 transistors.

24. An integrated assembly, comprising:

a memory array over a base;

vertically-extending digit lines associated with the memory array;

sense amplifiers under the memory array and coupled with the digit lines;

routing structures coupled to each of the digit lines and extending to Mux components; the Mux components being in one-to-one correspondence with the digit lines; each of the Mux components comprising a first transistor and a second transistor; the first transistors having first gates, first source/drain regions and second source/drain regions; the first gates gatedly coupling the first and second source/drain regions with one another; the second transistors having second gates, third source/drain regions and fourth source/drain regions; the second gates gatedly coupling the third and fourth source/drain regions with one another; the routing structures being coupled with the second and third source/drain regions; the first source/drain regions being coupled with second sense-amplifier-circuitry; the fourth source/drain regions being coupled with a voltage source; the first and second gates being coupled with Mux-Driver-circuitry configured to selectively activate/deactivate the first and second gates; and

wherein:

the first sense-amplifier-circuitry comprises a first threshold voltage associated therewith;

the second sense-amplifier-circuitry comprises a second threshold voltage associated therewith; and

the second threshold voltage is greater than the first threshold voltage.

25. An integrated assembly, comprising:

a memory array over a base;

vertically-extending digit lines associated with the memory array;

sense amplifiers under the memory array and coupled with the digit lines;

routing structures coupled to each of the digit lines and extending to Mux components; the Mux components being in one-to-one correspondence with the digit lines; each of the Mux components comprising a first transistor and a second transistor; the first transistors having first gates, first source/drain regions and second source/drain regions; the first gates gatedly coupling the first and second source/drain regions with one another; the second transistors having second gates, third source/drain regions and fourth source/drain regions; the second gates gatedly coupling the third and fourth source/drain regions with one another; the routing structures being coupled with the second and third source/drain regions; the first source/drain regions being coupled with second sense-amplifier-circuitry; the fourth source/drain regions being coupled with a voltage source; the first and second gates being coupled with Mux-Driver-circuitry configured to selectively activate/deactivate the first and second gates; and

wherein the sense amplifiers are local sense amplifiers, wherein the second sense-amplifier-circuitry comprises global sense amplifiers, and wherein at least 10 of the local sense amplifiers are associated with each of the global sense amplifiers.

26. An integrated assembly, comprising:

a memory array over a base;

vertically-extending digit lines associated with the memory array;

sense amplifiers under the memory array and coupled with the digit lines;

routing structures coupled to each of the digit lines and extending to Mux components; the Mux components being in one-to-one correspondence with the digit lines; each of the Mux components comprising a first transistor and a second transistor; the first transistors having first gates, first source/drain regions and second source/drain regions; the first gates gatedly coupling the first and second source/drain regions with one another; the second transistors having second gates, third source/drain regions and fourth source/drain regions; the second gates gatedly coupling the third and fourth source/drain regions with one another; the routing structures being coupled with the second and third source/drain regions; the first source/drain regions being coupled with second sense-amplifier-circuitry; the fourth source/drain regions being coupled with a voltage source; the first and second gates being coupled with Mux-Driver-circuitry configured to selectively activate/deactivate the first and second gates; and

wherein the sense amplifiers are local sense amplifiers, wherein the second sense-amplifier-circuitry comprises global sense amplifiers, and wherein at least 100 of the local sense amplifiers are associated with each of the global sense amplifiers.

27. An integrated assembly, comprising:

a memory array over a base;

vertically-extending digit lines associated with the memory array;

sense amplifiers under the memory array and coupled with the digit lines;

routing structures coupled to each of the digit lines and extending to Mux components; the Mux components being in one-to-one correspondence with the digit lines; each of the Mux components comprising a first transistor and a second transistor; the first transistors having first gates, first source/drain regions and second source/drain regions; the first gates gatedly coupling the first and second source/drain regions with one another; the second transistors having second gates, third source/drain regions and fourth source/drain regions; the second gates gatedly coupling the third and fourth source/drain regions with one another; the routing structures being coupled with the second and third source/drain regions; the first source/drain regions being coupled with second sense-amplifier-circuitry; the fourth source/drain regions being coupled with a voltage source; the first and second gates being coupled with Mux-Driver-circuitry configured to selectively activate/deactivate the first and second gates; and

wherein the sense amplifiers are local sense amplifiers, wherein the second sense-amplifier-circuitry comprises global sense amplifiers, and wherein at least 500 of the local sense amplifiers are associated with each of the global sense amplifiers.