Chip package with core embedded integrated devices
A chip package and methods for fabricating the same are provided that include integrated devices embedded and coupled in series between a lower surface of a package substrate and an integrated circuit die of the chip package. In some examples, the integrated devices are disposed side by side embedded in a common package substrate. In other examples, one of the series coupled integrated devices is embedded in a first package substrate while another of the series coupled integrated devices is embedded in a second package substrate that is stacked directly in contact with the first package substrate. The integrated devices may be passive and/or active integrated devices.
1 . A chip package, comprising:
a first package substrate, wherein a core of the first package substrate has a first cavity therein;
a second package substrate having a first surface facing a first surface of the first package substrate, wherein a core of the second package substrate has a second cavity therein, and wherein the first and second cavities are vertically aligned with one another;
an integrated circuit (IC) die adjacent to a second surface of the second package substrate;
a first integrated device (ID) disposed within the first cavity; and
a second IC disposed within the second cavity;
wherein the first and second IDs are connected in series with another and electrically connected to circuitry of the IC die.
2 . The chip package of claim 1 , wherein the first ID comprises an inductor, and the second ID comprises a capacitor.
3 . The chip package of claim 1 , wherein the first and second cavities are vertically aligned with one another and with the IC die.
4 . The chip package of claim 1 , wherein the first ID comprises a capacitor.
5 . The chip package of claim 1 , wherein the first ID comprises an inductor.
6 . The chip package of claim 5 , wherein the inductor comprises an air core inductor.
7 . The chip package of claim 5 , wherein the second ID comprises a capacitor.
8 . The chip package of claim 7 , wherein the first ID is part of a power network coupled to the circuitry of the IC die.
9 . The chip package of claim 1 , wherein the second package substrate is disposed between the first package substrate and the IC die, without an intervening interposer.
10 . The chip package of claim 8 , wherein a second surface of the first package substrate is configured to couple to a printed circuit board via a socket or solder balls.
11 . The chip package of claim 1 , wherein the first package substrate is thicker than the second package substrate.
12 . The chip package of claim 1 , wherein IC die is hybrid bonded to the second surface of the second package substrate.
13 . The chip package of claim 1 , wherein the first and second IDs each comprises one or more of a resistor, a capacitor, an inductor, an air core inductor, a coil, a balun, and an impedance matching element.
14 . A chip package, comprising:
a first package substrate, wherein a core of the first package substrate has first cavity therein;
a second package substrate having a first surface facing a first surface of the first package substrate, wherein a core of the second package substrate has a second cavity therein, and wherein the first and second cavities are vertically aligned with one another;
an integrated circuit (IC) die adjacent to a second surface of the second package substrate;
an inductor disposed within the first cavity;
a capacitor disposed within the second cavity;
wherein the inductor and the capacitor are connected in series with another and electrically connected to circuitry of the IC die, without an intervening interposer; and
an integrated circuit (IC) die adjacent to a second surface of the second package substrate.
15 . The chip package of claim 14 , wherein the inductor comprises an air core inductor.
16 . The chip package of claim 15 , wherein the core of the first package substrate is thicker than the core of the second package substrate.
17 . The chip package of claim 15 , wherein the capacitor and the air core inductor are part of a power network of the IC die.
18 . The chip package of claim 14 , wherein IC die is hybrid bonded to the second package substrate, and wherein circuitry of the first and second package substrates are connected without solder.
19 . A method, comprising:
disposing a first integrated device (ID) in a cavity of a first package substrate;
disposing a second integrated device (ID) in a cavity of a second package substrate;
vertically stacking the first package substrate, the second package substrate, and an integrated circuit (IC) die, with the second package substrate disposed between the first package substrate and the IC die, without an intervening interposer, wherein the cavities of the first and second package substrates are vertically aligned with one another; and
connecting the first and second IDs in series with one another and to circuitry of the IC die.
20 . The method of claim 19 , wherein:
the first ID comprises an inductor;
the second ID comprises a capacitor; and
the first and second IDs form part of a power delivery network of the IC die.