IP Library Granted Patent US 12,684,910
Granted Patent B2
US 12,684,910 · App. 17/889,922 · Granted Jul 14, 2026

Metallic layer for dimming light-emitting diode chips

Inventors: Steven Wuester (Wake Forest, NC); Seth Joseph Balkey (Durham, NC); Colin Stuart (Durham, NC); Peter Andrews (Durham, NC)
Assignee: CreeLED, Inc.
H10H20/833H10H20/01H10H20/84
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Quick Facts
Patent No.
US 12,684,910
App. No.
17/889,922
Granted
Jul 14, 2026
Kind
B2
Abstract

Solid-state lighting devices including light-emitting diodes (LEDs) and a semi-transparent metallic layer deposited on an LED chip that can dim a light output of the LED chip are disclosed. The thickness of the semi-transparent metal layer can be adjusted based on the desired dimming level. In an embodiment, the metallic layer can be deposited on top of a passivation layer over the LED structure, so that the metallic layer is not electrically coupled to the LED. The metallic layer can additionally cover the mesa sidewalls of the LED structure. The metallic layer can be titanium, or platinum, or other suitable metals in other embodiments. In an embodiment, the metallic layer can be deposited on to the passivation layer, where a length of time the metallic layer is deposited, can be based on the amount of dimming desired.

Claims (33)

1 . A light-emitting diode (LED) chip, comprising:

an active LED structure comprising an n-type layer, a p-type layer, and an active layer that is between the n-type layer and the p-type layer, the active LED structure forming a mesa with mesa sidewalls that define a perimeter of the active LED structure;

an electrical connection to the n-type layer from a first side of the active LED structure;

a metallic layer that is partially transparent to wavelengths of light generated by the active LED structure, wherein the metallic layer is on a second side of the active LED structure that is opposite the first side, and wherein the metallic layer is patterned to not cover a street or pad region of the LED chip; and

a passivation layer between the metallic layer and the active LED structure, so that the metallic layer is electrically isolated from the active LED structure.

2 . The LED chip of claim 1 , wherein the mesa sidewalls are covered by the passivation layer and the metallic layer.

3 . The LED chip of claim 1 , wherein the metallic layer is configured to dim light emitted by the active LED structure.

4 . The LED chip of claim 3 , wherein an amount of light dimmed by the metallic layer corresponds to a thickness of the metallic layer.

5 . The LED chip of claim 1 , wherein the metallic layer is at least one of titanium or platinum.

6 . The LED chip of claim 1 , wherein the metallic layer is sputter deposited onto the passivation layer.

7 . The LED chip of claim 1 , wherein the metallic layer is patterned with a predefined pattern.

8 . The LED chip of claim 1 , wherein a first thickness of the metallic layer over a top of the active LED structure is different from a second thickness of the metallic layer over the mesa sidewalls of the active LED structure.

9 . A light-emitting diode (LED) chip, comprising:

a carrier submount;

an active LED structure bonded to the carrier submount, the active LED structure comprising an n-type layer, a p-type layer, and an active layer arranged between the n-type layer and the p-type layer, the active LED structure forming a mesa with mesa sidewalls that define a perimeter of the active LED structure;

a metallic layer that is partially transparent to wavelengths of light generated by the active LED structure, wherein the metallic layer is on an opposite side of the active LED structure than the carrier submount, and wherein the metallic layer is patterned to not cover a street or pad region of the LED chip; and

a dielectric layer between the metallic layer and the active LED structure, so that the metallic layer is electrically isolated from the active LED structure.

10 . The LED chip of claim 9 , wherein the mesa sidewalls are covered by the dielectric layer and the metallic layer.

11 . The LED chip of claim 9 , wherein the metallic layer is configured to dim light emitted by the active LED structure.

12 . The LED chip of claim 11 , wherein an amount of light dimmed by the metallic layer corresponds to a thickness of the metallic layer.

13 . The LED chip of claim 9 , wherein the metallic layer is at least one of titanium or platinum.

14 . The LED chip of claim 9 , wherein the metallic layer is sputter deposited onto the dielectric layer.

15 . The LED chip of claim 9 , wherein the metallic layer is patterned with a predefined pattern.

16 . The LED chip of claim 9 , wherein the dielectric layer is silicon nitride.

17 . The LED chip of claim 9 , wherein a first thickness of the metallic layer over a top of the active LED structure is different from a second thickness of the metallic layer over the mesa sidewalls of the active LED structure.

18 . A method for fabricating a light-emitting diode (LED) chip, comprising:

forming an active LED structure over a carrier submount, the active LED structure comprising an n-type layer, a p-type layer, and an active layer that is between the n-type layer and the p-type layer, the active LED structure forming a mesa with mesa sidewalls that define a perimeter of the active LED structure;

depositing a passivation layer over the active LED structure; and

depositing a metallic layer over the passivation layer that is partially transparent to wavelengths of light generated by the active LED structure, wherein the metallic layer is electrically isolated from the active LED structure, wherein the metallic layer is configured to dim a light emitted by the active LED structure, and wherein the metallic layer is patterned to not cover a street or pad region of the LED chip.

19 . The method of claim 18 , further comprising:

depositing the metallic layer to a predetermined thickness based on a predetermined dimming level.

20 . The method of claim 18 , further comprising:

depositing the metallic layer in a predetermined pattern corresponding to an emission pattern.

Assignments (2)
PATENT SECURITY AGREEMENT Recorded Jun 30, 2025
From: CREELED, INC.; PENGUIN SOLUTIONS CORPORATION (DE); SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; SMART MODULAR TECHNOLOGIES, INC.; PENGUIN COMPUTING, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 071755/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2022
From: WUESTER, STEVEN; BALKEY, SETH JOSEPH; STUART, COLIN; ANDREWS, PETER
To: CREELED, INC.
Reel/Frame 061437/0118 →
Continuity (1)
Related Publication 20240063344A1 · Feb 22, 2024
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