Neural network compute tile
A computing unit is disclosed, comprising a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs one or more computations associated with at least one element of a data array, the one or more computations being performed by the MAC operator and comprising, in part, a multiply operation of the input activation received from the data bus and a parameter received from the second memory bank.
1. A system comprising a plurality of computing tiles, wherein each computing tile of the plurality of computing tiles comprises:
a first memory bank having a first data width;
a second memory bank having a second data width that is larger than the first data width;
a first computing unit comprising a first register, the first computing unit being configured to
store instructions according to a first instruction type in the first register, and
execute the instructions according to the first instruction type; and
a second computing unit comprising a second register, the second computing unit being configured to
store instructions according to a second instruction type in the second register, and
execute the instructions according to the second instruction type.
2. The system of claim 1 , wherein the first memory bank comprises a memory arbiter configured to determine which of the first computing unit and the second computing unit can access memory resources of the first memory bank.
3. The system of claim 1 , wherein each of the first register and the second register comprises a first-in first-out control scheme that prioritizes execution of instructions stored in the first register and the second register, respectively.
4. The system of claim 1 , wherein the first computing unit is configured to write input activation parameters to the first memory bank, and
wherein the second computing unit is configured to write weight parameters to the second memory bank.
5. The system of claim 1 , further comprising an arithmetic computation unit, wherein the arithmetic computation unit comprises an array of arithmetic computation cells.
6. The system of claim 5 , wherein each arithmetic computation cell of the array of arithmetic computation cells is configured to perform a multiple-accumulate operation.
7. The system of claim 1 , wherein the first computing unit is configured to load data parameters from a plurality of tensor traversal units at the beginning of a tensor operation.
8. The system of claim 7 , wherein the data parameters comprise counter values, limit values, and stride values.
9. A method for operating a computing tile, wherein the computing tile comprises a first memory bank having a first data width, a second memory bank having a second data width that is larger than the first data width, a first computing unit comprising a first register, a second computing unit comprising a second register, wherein the method comprises:
storing instructions according to a first instruction type in the first register;
execute the instructions according to the first instruction type;
storing instructions according to a second instruction type in the second register, and
execute the instructions according to the second instruction type.
10. The method of claim 9 , wherein the first memory bank comprises a memory arbiter, and the method comprises determining, by the memory arbiter, which of the first computing unit and the second computing unit can access memory resources of the first memory bank.
11. The method of claim 9 , wherein each of the first register and the second register comprises a first-in first-out control scheme that prioritizes execution of instructions stored in the first register and the second register, respectively.
12. The method of claim 9 , comprising:
writing input activation parameters to the first memory bank; and
write weight parameters to the second memory bank.
13. The method of claim 9 , wherein the computing tile comprises an arithmetic computation unit, wherein the arithmetic computation unit comprises an array of arithmetic computation cells.
14. The method of claim 13 , comprising performing, by at least one arithmetic computation cell of the array of arithmetic computation cells, a multiple-accumulate operation.
15. The method of claim 9 , comprising loading, by the first computing unit, data parameters from a plurality of tensor traversal units at the beginning of a tensor operation.
16. The method of claim 15 , wherein the data parameters comprise counter values, limit values, and stride values.