Integration of solar cell and image sensor
The present disclosure provides an integrated circuit (IC) structure with a solar cell and an image sensor array. An integrated structure according to the present disclosure includes a first substrate including a plurality of photodiodes, an interconnect structure disposed on the first substrate, a first bonding layer disposed on the interconnect structure, a second bonding layer disposed on the first bonding layer, a second substrate disposed on the second bonding layer, and a transparent conductive oxide layer disposed on the second substrate.
1. An integrated circuit (IC) structure, comprising:
a first substrate comprising a plurality of photodiodes;
an interconnect structure disposed on the first substrate;
a first bonding layer disposed on the interconnect structure;
a second bonding layer disposed on the first bonding layer;
a second substrate disposed on the second bonding layer; and
a transparent conductive oxide layer disposed on the second substrate.
2. The IC structure of claim 1 , wherein the second substrate comprises a textured top region in direct contact with the transparent conductive oxide layer.
3. The IC structure of claim 2 , wherein the textured top region comprises silicon and an n-type dopant.
4. The IC structure of claim 1 ,
wherein the first bonding layer comprises a first plurality of conductive pads embedded in a first dielectric layer,
wherein the second bonding layer comprises a second plurality of conductive pads embedded in a second dielectric layer,
wherein the first plurality of conductive pads are vertically aligned with the second plurality of conductive pads.
5. The IC structure of claim 4 , wherein the interconnect structure comprises a capacitor structure that includes a bottom metal layer, an insulator layer disposed on the bottom metal layer, and a top metal layer disposed on the insulator layer.
6. The IC structure of claim 5 ,
wherein the first substrate further comprises an inverter,
wherein the top metal layer is in electrical communication with at least one of the second plurality of conductive pads,
wherein the bottom metal layer is in electrical communication with the inverter.
7. The IC structure of claim 1 , further comprising:
an antireflection coating on the transparent conductive oxide layer; and
a metal grid disposed over the antireflection coating.
8. The IC structure of claim 1 ,
wherein the first substrate has a first thickness,
wherein the second substrate has a second thickness greater than the first thickness.
9. The IC structure of claim 8 ,
wherein the first thickness is between about 1 μm and about 8 μm,
wherein the second thickness is between about 150 μm and about 500 μm.
10. A structure, comprising:
a plurality of microlens features;
a color filter array disposed on the plurality of microlens features;
a first metal grid over the color filter array;
a first substrate over the first metal grid;
an interconnect structure over the first substrate; and
a second substrate over the interconnect structure,
wherein the second substrate comprises a top texture region,
wherein the interconnect structure comprises a capacitor structure.
11. The structure of claim 10 , further comprising:
a first bonding layer disposed on the interconnect structure; and
a second bonding layer disposed on the first bonding layer.
12. The structure of claim 11 ,
wherein the first bonding layer comprises a first plurality of conductive pads embedded in a first dielectric layer,
wherein the second bonding layer comprises a second plurality of conductive pads embedded in a second dielectric layer,
wherein the first plurality of conductive pads are vertically aligned with the second plurality of conductive pads.
13. The structure of claim 12 , wherein the second bonding layer comprises a plurality of reflective features configured to reflect electromagnetic radiation into the second substrate.
14. The structure of claim 10 ,
wherein the first substrate comprises a plurality of photodiodes and an inverter,
wherein the plurality of photodiodes are separated from one another by deep trench isolation (DTI) features.
15. The structure of claim 10 , wherein the interconnect structure comprises a capacitor structure that includes a bottom metal layer, an insulator layer over the bottom metal layer, and a top metal layer over the insulator layer.
16. A device structure, comprising:
an image sensor array;
an interconnect structure over the image sensor array;
a bonding layer over the interconnect structure;
a plurality of redirecting features disposed in the bonding layer; and
a substrate disposed over the bonding layer,
wherein each of the plurality of redirecting features comprises a textured surface facing the substrate,
wherein the substrate comprises a scallop-like surface texture on a surface facing away from the bonding layer.
17. The device structure of claim 16 , wherein the plurality of redirecting features comprise copper (Cu).
18. The device structure of claim 16 , wherein the substrate comprises silicon, germanium, or a III-V semiconductor material.
19. The device structure of claim 16 , wherein the interconnect structure comprises a capacitor structure.
20. The device structure of claim 16 , wherein the bonding layer comprises silicon oxide or silicon oxynitride.