Integration of nanosheets with bottom dielectric isolation and ideal diode
Techniques for co-integrating gate-all-around nanosheet devices having bottom dielectric isolation with an ideal vertical P-N-P diode on a common substrate are provided. In one aspect, a semiconductor structure includes: a diode in a first region of a bulk substrate, where the diode includes P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers; and a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate. The nanosheet device can include nanosheet channels and gates that surround a portion of each of the nanosheet channels in a gate-all-around configuration. A method of fabricating the present semiconductor structures is also provided.
1. A semiconductor structure, comprising:
a diode in a first region of a bulk substrate, wherein the diode comprises P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed directly on a top layer of the P-N-P vertical implanted layers; and
a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate.
2. The semiconductor structure of claim 1 , wherein the P-N-P vertical implanted layers comprise:
a Psub implant in the bulk substrate;
an Nwell implant in the bulk substrate over the Psub implant; and
a P+ implant in the second region of the bulk substrate over the Nwell implant.
3. The semiconductor structure of claim 1 , further comprising:
multiple source/drain contacts to the single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers.
4. The semiconductor structure of claim 1 , wherein the single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers has a width W of from about 2 μm to about 5 μm, and a length L of from about 3 μm to about 10 μm.
5. The semiconductor structure of claim 1 , wherein the single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers has a varying height H.
6. The semiconductor structure of claim 1 , further comprising:
a ring of a same material as the bottom dielectric isolation layer surrounding the single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers.
7. The semiconductor structure of claim 1 , further comprising:
gates contacting opposite ends of the single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers.
8. A semiconductor structure, comprising:
a diode in a first region of a bulk substrate, wherein the diode comprises P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed directly on a top layer of the P-N-P vertical implanted layers; and
a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate, wherein the nanosheet device comprises nanosheet channels and gates that surround a portion of each of the nanosheet channels in a gate-all-around configuration.
9. The semiconductor structure of claim 8 , wherein the P-N-P vertical implanted layers comprise:
a Psub implant in the bulk substrate;
an Nwell implant in the bulk substrate over the Psub implant; and
a P+ implant in the first region of the bulk substrate over the Nwell implant.
10. The semiconductor structure of claim 8 , further comprising:
multiple source/drain contacts to the single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers.
11. The semiconductor structure of claim 8 , wherein the single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers has a width W of from about 2 μm to about 5 μm, and a length L of from about 3 μm to about 10 μm.
12. The semiconductor structure of claim 8 , wherein the single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers has a varying height H.
13. The semiconductor structure of claim 8 , further comprising:
a ring of a same material as the bottom dielectric isolation layer surrounding the single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers.
14. The semiconductor structure of claim 8 , further comprising:
first gates contacting opposite ends of the single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers, wherein the gates that surround the portion of each of the nanosheet channels comprise second gates.
15. The semiconductor structure of claim 14 , wherein the single source/drain region epitaxial material contacts both the bulk substrate and patterned portions of the nanosheet channels under the first gates.
16. The semiconductor structure of claim 14 , wherein the first gates and the second gates comprise a same combination of materials.
17. A method of fabricating a semiconductor structure, the method comprising:
performing a Psub implant in a bulk substrate, including in a first region of the bulk substrate;
performing an Nwell implant in the bulk substrate over the Psub implant;
forming a nanosheet device with nanosheet channels and a bottom dielectric isolation layer in a second region of the bulk substrate;
performing a P+ implant in the first region of the bulk substrate over the Nwell implant; and
concurrently forming a source/drain region epitaxial material directly on the P+ implant in the first region of the bulk substrate and in source/drain regions of the nanosheet device in the second region of the bulk substrate.
18. The method of claim 17 , further comprising:
forming a nanosheet stack on the first region and the second region of the bulk substrate; and
selectively removing the nanosheet stack from the first region of the bulk substrate.
19. The method of claim 17 , further comprising:
forming a ring of a same material as the bottom dielectric isolation layer surrounding the source/drain region epitaxial material in the first region of the bulk substrate.
20. The method of claim 17 , further comprising:
concurrently forming first gates in the first region of the bulk substrate that contact opposite ends of the source/drain region epitaxial material, and second gates in the second region of the bulk substrate that surround a portion of each of the nanosheet channels in a gate-all-around configuration.