Energy efficient electrical pulse generating device
According to another disclosed embodiment, an energy efficient implantable neurostimulator for delivering one or more electrical pulses to a target region within a patient's body is provided. The neurostimulator includes a converter for generating the stimulation current, wherein the converter includes a voltage increasing circuit and a voltage reducing circuit. The stimulator may also include a current source that includes a pair of cascode arranged transistors that are controlled to maintain an amplitude of the stimulation current substantially constant. The neurostimulator may also include a bias voltage power supply that powers a selecting circuit for selecting one of the voltage increasing or voltage decreasing circuits.
1 . An energy efficient device for delivering one or more electrical pulses to a target region within a patient's body, the device comprising:
a housing;
a controller located in the housing;
an energy source located in the housing; and
a stimulation circuit located in the housing, wherein the stimulation circuit generates a stimulation current that provides the one or more electrical pulses, and wherein the stimulation circuit includes a current source;
wherein the energy source provides a voltage to the stimulation circuit;
wherein the current source includes a pair of cascode arranged transistors that are controlled to maintain an amplitude of the stimulation current substantially constant, wherein the controller is configured to control the stimulation circuit to minimize the voltage across one of the pair of cascode arranged transistors in order to reduce an amount of energy withdrawn from the energy source while the current source operates to provide the substantially constant stimulation current.
2 . The energy efficient device of claim 1 , wherein the stimulation current includes a set of phases including at least a first phase and a second phase and wherein the current source includes a set of current sources corresponding to each phase in the set of phases including at least a phase one current source and a phase two current source.
3 . The energy efficient device of claim 2 , wherein the phase one current source includes the pair of cascode arranged transistors, and the phase two current source includes an additional pair of cascode arranged transistors.
4 . The energy efficient device of claim 3 , wherein a transistor of the pair of cascode arranged transistors of the phase one current source includes a first control input configured to control the current allowed through the pair of cascode arranged transistors of the phase one current source.
5 . The energy efficient device of claim 4 , wherein the first control input is controlled via a first control voltage applied to the first control input, wherein the control voltage is maintained by a control voltage holding capacitor coupled to the first control input of the transistor of the pair of cascode arranged transistors of the phase one current source.
6 . The energy efficient device of claim 5 , wherein the control voltage corresponds to the amplitude of the stimulation current.
7 . The energy efficient device of claim 4 , wherein a transistor of the additional pair of cascode arranged transistors of the phase two current source includes a second control input configured to control the current allowed through the additional pair of cascode arranged transistors of the phase two current source.
8 . The energy efficient device of claim 1 , further comprising wherein a gate input of one of the pair of cascode arranged transistors receives a control voltage that directly defines the amplitude of the stimulation current, the control voltage being maintained by a capacitor coupled to the gate input so as to hold the bias voltage applied to that transistor.
9 . An implantable neurostimulator for delivering an electrical pulse to a target region within a patient's body, the neurostimulator comprising:
a housing;
a controller located in the housing;
an energy source located in the housing;
a stimulation circuit located in the housing, wherein the stimulation circuit generates a stimulation current that provides the electrical pulse, wherein the stimulation circuit includes:
a converter for generating the stimulation current;
a current source in electrical communication with the converter; and
wherein the current source includes a pair of cascode arranged transistors that are controlled to maintain an amplitude of the stimulation current substantially constant, wherein the controller is configured to control the pair of cascode transistors to minimize a voltage across one of the pair of cascode arranged transistors in order to reduce an amount of energy withdrawn from the energy storage device while the current source operates to provide the substantially constant stimulation current.
10 . The neurostimulator of claim 9 , wherein the stimulation current has two phases and wherein the current source includes a phase one current source and a phase two current source.
11 . The neurostimulator of claim 10 , wherein the phase one current source includes the pair of cascode arranged transistors, and the phase two current source includes an additional pair of cascode arranged transistors.
12 . The neurostimulator of claim 11 , wherein a transistor of the pair of cascode arranged transistors of the phase one current source includes a first control input configured to control the current allowed through the pair of cascode arranged transistors of the phase one current source.
13 . The neurostimulator of claim 12 , wherein the first control input is controlled via a first control voltage applied to the first control input, wherein the control voltage is maintained by a control voltage holding capacitor coupled to the first control input of the transistor of the pair of cascode arranged transistors of the phase one current source.
14 . The neurostimulator of claim 13 , wherein the control voltage corresponds to the amplitude of the stimulation current.
15 . The neurostimulator of claim 12 , wherein a transistor of the additional pair of cascode arranged transistors of the phase two current source includes a second control input configured to control the current allowed through the additional pair of cascode arranged transistors of the phase two current source.