IP Library › Granted Patent US 12,232,436
Granted Patent B2
US 12,232,436 · App. 17/896,213 · Granted Feb 18, 2025

Information processing device and method of driving information processing device

Inventors: Hisashi Shima (Tsukuba, JP); Yasuhisa Naitoh (Tsukuba, JP); Hiroyuki Akinaga (Tsukuba, JP); Makoto Takahashi (Tsukuba, JP)
Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
H10N70/8833G06N3/065G11C13/0007H10B63/22H10N70/826H10N70/841G11C2213/32G11C2213/55
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,232,436
App. No.
17/896,213
Granted
Feb 18, 2025
Kind
B2
Abstract

An information processing device, including a resistive analog neuromorphic device element having a pair of electrodes and an oxide layer provided between the pair of electrodes, and a parallel circuit having a low resistance component and a capacitance component. The parallel circuit and the resistive analog neuromorphic device element are connected in series.

Claims (24)

1. An information processing device, comprising:

a first resistive analog neuromorphic device element, having:

a pair of electrodes, and

an oxide layer provided between the pair of electrodes, the oxide layer including a plurality of stacked layers of differing resistivities; and

a second resistive analog neuromorphic device element, having:

a low resistance component, and

a capacitance component, wherein

the first and second resistive analog neuromorphic device elements are connected in series to form a device element having a resistance value that is variable.

2. The information processing device according to claim 1 , wherein

the pair of electrodes in the first resistive analog neuromorphic device element includes an upper electrode and a lower electrode,

the second resistive analog neuromorphic device element includes an upper electrode, a lower electrode and an oxide layer provided therebetween,

the upper electrode, the lower electrode, and the oxide layer in the second resistive analog neuromorphic device element configuring a single resistive analog neuromorphic device element in which the low resistance component and the capacitance component are connected in parallel, and

the lower electrodes of the first and second resistive analog neuromorphic device elements are connected, so as to form a circuit system from the upper electrode of the first resistive analog neuromorphic device element to the upper electrode of the second resistive analog neuromorphic device element.

3. The information processing device according to claim 1 , wherein

a resistivity of one of the plurality of stacked layers is less than 1000 mOhm cm, and

a resistivity of another of the plurality of stacked layers is at least 1000 mOhm cm.

4. The information processing device according to claim 1 , further comprising:

a plurality of resistive analog neuromorphic device elements, including the first and second resistive analog neuromorphic device elements, that are provided at different planar positions on a substrate, and

each of the plurality of resistive analog neuromorphic device elements has a lower electrode, and a pair of the lower electrodes that are adjacent to each other are connected to each other.

5. The information processing device according to claim 2 , further comprising a substrate, wherein

sequentially from the substrate, the lower electrode, the oxide layer, an intermediate electrode, the oxide layer, and the upper electrode are stacked at a single planar position on the substrate, as the first resistive analog neuromorphic device element.

6. A method of driving an information processing device having a first resistive analog neuromorphic device element that has a pair of electrodes and an oxide layer provided between the pair of electrodes, the oxide layer including a plurality of stacked layers of differing resistivities, the method comprising:

connecting a second resistive analog neuromorphic device element in series to the first resistive analog neuromorphic device element, the second resistive analog neuromorphic device element having a low resistance component and a capacitance component; and

applying a voltage to thereby provide a variable resistance value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2022
From: SHIMA, HISASHI; NAITOH, YASUHISA; AKINAGA, HIROYUKI; TAKAHASHI, MAKOTO
To: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
Reel/Frame 060909/0358 →
Priority Claims (1)
JP 2020-032407 · Feb 27, 2020 · national
Continuity (2)
Continuation PCTJP2021006485 · Feb 19, 2021
Related Publication 20220407003A1 · Dec 22, 2022
References Cited (41)
US 8531862B2 · Roest · 2013 [cited by applicant]
US 8673203B2 · Clark · 2014 [cited by examiner]
US 9269903B2 · Nishioka · 2016 [cited by applicant]
US 9864950B2 · Datta · 2018 [cited by examiner]
US 10392243B2 · Almeida Loya · 2019 [cited by examiner]
US 10403816B2 · Reid · 2019 [cited by examiner]
US 10658587B2 · Reid · 2020 [cited by examiner]
US 10861545B2 · Dalgaty · 2020 [cited by examiner]
US 11068777B2 · Bedell · 2021 [cited by examiner]
US 11551749B2 · Bibes · 2023 [cited by examiner]
US 11586884B2 · Yang · 2023 [cited by examiner]
US 11625590B2 · Cho · 2023 [cited by examiner]
US 11636316B2 · Shifren · 2023 [cited by examiner]
US 11861488B1 · Yi · 2024 [cited by examiner]
US 20100276684A1 · Shima et al. · 2010 [cited by applicant]
US 20110051500A1 · Takagi et al. · 2011 [cited by applicant]
US 20140146594A1 · Hayakawa et al. · 2014 [cited by applicant]
US 20180076386A1 · Reid et al. · 2018 [cited by applicant]
US 20180082168A1 · Marukame et al. · 2018 [cited by applicant]
US 20190229770A1 · Gangadharrao et al. · 2019 [cited by examiner]
US 20190244088A1 · Yang et al. · 2019 [cited by applicant]
US 20210349693A1 · Ito · 2021 [cited by examiner]
US 20220130900A1 · Terasaki · 2022 [cited by examiner]
US 20220261559A1 · Shibata · 2022 [cited by examiner]
EP 0775932B1 · 2001 [cited by applicant]
JP 2007293969A · 2007 [cited by applicant]
JP 2009135461A · 2009 [cited by applicant]
JP 2018049887A · 2018 [cited by applicant]
TW 201242232A · 2012 [cited by applicant]
TW 201619680A · 2016 [cited by applicant]
TW 201721856A · 2017 [cited by applicant]
WO 2010064446A1 · 2010 [cited by applicant]
WO 2012169194A1 · 2012 [cited by applicant]
WO 2016153515A1 · 2016 [cited by applicant]
Japanese Office Action dated Aug. 22, 2023, in the counterpart Japanese Patent Application No. 2020-032407. [cited by applicant]
Hisashi Shima et al., “Electrode Material Dependence of Resistance Change Behavior in Ta2O5 Resistive Analog Neuromorphic Device”, IEEE Journal of the Electron Devices Society, Oct. 17, 2018, vol. 6, pp. 1220-1226. [cited by applicant]
International Search Report for PCT/JP2021/006485, mailed on May 25, 2021. [cited by applicant]
Written Opinion of the International Searching Authority for PCT/JP2021/006485, mailed on May 25, 2021. [cited by applicant]
Zhongrui Wang, 23 others, “Capacitive neural network with neuro-transistors”, [online], Aug. 10, 2018, nature communications, [searched on Feb. 6, 2020], Internet. [cited by applicant]
Taiwanese Office Action issued on Sep. 28, 2021, for the corresponding Taiwan patent application No. 110106641. [cited by applicant]
Chinese Office Action dated Oct. 31, 2024, in the counterpart Chinese Patent Application No. 202180017574.8. [cited by applicant]