Semiconductor memory device and methods of manufacturing and operating the same
A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a stack structure by alternately stacking a plurality of interlayer insulating layer and a plurality of sacrificial layers on a substrate;
forming a plurality of holes penetrating the stack structure in a vertical direction; and
sequentially forming a blocking insulating layer, a charge storage layer, an emission preventing layer, a tunnel insulating layer, and a channel layer on a sideman of each of the plurality of holes.
2. The method of claim 1 , wherein the emission preventing layer is formed as a quantum dot monolayer.
3. The method of claim 1 , wherein the emission preventing layer is formed as a metal silicide layer.
4. The method of claim 3 , wherein the metal silicide layer is formed by sequentially depositing a tungsten thin film and a silicon thin film on a sidewall of the charge storage layer and then performing a metal heat treatment process.
5. The method of claim 3 , wherein the metal silicide layer is formed by depositing a tungsten silicide layer on a sidewall of the charge storage layer through a CVD or ALD process and then performing a metal heat treatment process.
6. The method of claim 1 , wherein the emission preventing layer is formed as a silicon layer.
7. The method of claim 6 , wherein the silicon layer is formed by forming an SiO 2 layer or an SiON layer on the sidewall of the charge storage layer and then performing a metal heat treatment process (RTA) under an N 2 atmosphere.
8. The method of claim 1 , further comprising forming a compensation charge storage layer on a sidewall of each of the plurality of holes before the blocking insulating layer is formed.
9. The method of claim 8 , wherein the compensation charge storage layer is formed as a multi-layer, and at least one layer included in the multi-layer forms a trap.
10. The method of claim 9 , wherein the at least one layer is formed as Al 2 O 3 , and a trap is formed through a redox mechanism by adjusting a composition ratio of Al and O.
11. The method of claim 8 , wherein the compensation charge storage layer includes a layer including at least one of Al 2 O 3 , HfO, ZrO, Ta 2 O 3 , HfTaxOy, LaHfO, and HfSiO.