Hybrid precision MS decoder to reduce gate-count for long codes

1. A method for operating an MS decoder comprising:

determining an operation mode of the MS decoder based on code lengths of codewords being decoded, the MS decoder having a channel value memory storing data bits;

for each variable node, calculating a variable to check node V 2 C message including check information; and

storing, in a check node unit CNU memory, the check information associated with the calculated V 2 C message according to the operation mode,

wherein the check information includes full information when the operation mode is a high bit precision mode for a first codeword length, and includes partial information when the operation mode is a low bit precision mode for a second codeword length longer than the first codeword length, and

wherein the MS decoder supports on-the-fly code-length changes by changing the operational mode.

2. The method of claim 1 , wherein the full information includes, for each checksum, a min 1 value, a min 1 index, a min 2 value, a min 2 index, and a checksum.

3. The method of claim 2 , wherein

the min 1 value and the min 2 value are stored in the check node unit CNU memory at a 4 bit precision,

the min 1 index and the min 2 index are stored in the check node unit CNU memory at a 6 bit precision, and

the checksum is stored at a 1 bit precision.

4. The method of claim 2 , wherein, for the full information, the operation mode operates in a 4 KB mode.

5. The method of claim 1 , wherein the partial information includes, for each checksum, a min 1 value, a min 1 index, a min 2 value, and a checksum.

6. The method of claim 5 , wherein

the min 1 value and the min 2 value are stored in the check node unit CNU memory at a 2 or 3 bit precision,

the min 1 index is stored in the check node unit CNU memory at a 6 bit precision, and

the checksum is stored at a 1 bit precision.

7. The method of claim 5 , wherein, for the partial information, the operation mode operates in a 8 KB or a 16 KB mode.

8. The method of claim 1 , wherein the CNU memory in the MS decoder operates as part of a MS LDPC decoder.

9. The method of claim 8 , wherein iterations of MS LDPC decoding continue until a maximum number of iterations is reached or until a LDPC codeword is successfully decoded.

10. The method of claim 9 ,

wherein the channel value memory and the CNU memory work in the high bit precision mode when the codewords have the first codeword length,

wherein the channel value memory and the CNU memory work in the low bit precision mode when the codewords have the second codeword length longer than the first codeword length, and

wherein the MS decoder in the low bit precision mode has a reduced gate count compared to the MS decoder operating entirely in the high bit precision mode.

11. A memory system comprising:

a memory device;

a controller in communication with and configured to control the memory device; and

a min-sum (MS) decoder in communication with a storage of the memory device, the MS decoder having a channel value memory storing data bits,

wherein the MS decoder is configured to:

determine an operation mode of the MS decoder based on code lengths of codewords being decoded for each variable node, calculate a variable to check node V 2 C message including check information; and

store, in a check node unit CNU memory, the check information associated with the calculated V 2 C message according to an operation mode of the MS decoder,

wherein the check information includes full information when the operation mode is a high bit precision mode for a first codeword length, and includes partial information when the operation mode is a low bit precision mode for a second codeword length longer than the first codeword length, and

wherein the MS decoder supports on-the-fly code-length changes by changing the operational mode.

12. The system of claim 11 , wherein the full information includes, for each checksum, a min 1 value, a min 1 index, a min 2 value, a min 2 index, and a checksum.

13. The system of claim 12 , wherein

the min 1 value and the min 2 value are stored in the check node unit CNU memory at a 4 bit precision,

the min 1 index and the min 2 index are stored in the check node unit CNU memory at a 6 bit precision, and

the checksum is stored at a 1 bit precision.

14. The system of claim 12 , wherein, for the full information, the operation mode operates in a 4 KB mode.

15. The system of claim 11 , wherein the partial information includes, for each checksum, a min 1 value, a min 1 index, a min 2 value, and a checksum.

16. The system of claim 15 , wherein

the min 1 value and the min 2 value are stored in the check node unit CNU memory at a 2 or 3 bit precision,

the min 1 index is stored in the check node unit CNU memory at a 6 bit precision, and

the checksum is stored at a 1 bit precision.

17. The system of claim 15 , wherein, for the partial information, the operation mode operates in a 8 KB or a 16 KB mode.

18. The system of claim 11 , wherein the CNU memory in the MS decoder operates as part of a MS LDPC decoder.

19. The system of claim 18 , wherein iterations of MS LDPC decoding continue until a maximum number of iterations is reached or until a LDPC codeword is successfully decoded.

20. The system of claim 19 ,

wherein the channel value memory and the CNU memory work in the high bit precision mode when the codewords have the first codeword length,

wherein the channel value memory and the CNU memory work in the low bit precision mode when the codewords have the second codeword length longer than the first codeword length, and

wherein the MS decoder in the low bit precision mode has a reduced gate count compared to the MS decoder operating entirely in the high bit precision mode.