IP Library › Granted Patent US 12,101,884
Granted Patent B2
US 12,101,884 · App. 17/901,997 · Granted Sep 24, 2024

Isolator

Inventors: Yusuke Imaizumi (Kawasaki Kanagawa, JP); Jia Liu (Yokohama Kanagawa, JP); Yoshinari Tamura (Yokohama Kanagawa, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H05K1/165H05K1/111H05K1/115H05K1/14H01L23/49513H01L24/32H01L24/48H01L24/73H01L2224/32245H01L2224/48227H01L2224/73265
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Quick Facts
Patent No.
US 12,101,884
App. No.
17/901,997
Granted
Sep 24, 2024
Kind
B2
Abstract

According to one embodiment, an isolator includes a first wiring board and a second wiring board. The first wiring board includes a first insulating layer including first and second principal surfaces; a first coil provided on the first principal surface; and a first pad provided on the first principal surface and electrically connected to the first coil. The second wiring board includes a second insulating layer including third and fourth principal surfaces; a second coil provided on the third principal surface; and a second pad provided on the fourth principal surface and electrically connected to the second coil. The first and second coils are arranged in such a manner as to face each other, and an external size of the second wiring board is smaller than an external size of the first wiring board.

Claims (50)

1. An isolator comprising:

a first wiring board including:

a first insulating layer including a first principal surface and a second principal surface opposite to the first principal surface;

a first coil provided on the first principal surface; and

a first pad that is provided on the first principal surface and electrically connected to the first coil, and

a second wiring board including:

a second insulating layer including a third principal surface and a fourth principal surface opposite to the third principal surface;

a second coil provided on the third principal surface; and

a second pad that is provided on the fourth principal surface and electrically connected to the second coil,

wherein

the first coil and the second coil are arranged in such a manner as to face each other, and

an external size of the second wiring board is smaller than an external size of the first wiring board.

2. The isolator according to claim 1 , wherein

the first pad of the first wiring board is arranged at a height between the first coil and the second coil.

3. The isolator according to claim 1 , wherein

a distance from the first principal surface of the first insulating layer to the first pad is shorter than a distance from the first principal surface of the first insulating layer to the second pad.

4. The isolator according to claim 1 , wherein

the first principal surface of the first insulating layer includes a region not overlapping the third principal surface of the second insulating layer, and the first pad is arranged in the region.

5. The isolator according to claim 1 , further comprising:

a third insulating layer provided between the first coil and the second coil,

wherein the third insulating layer includes polyimide.

6. The isolator according to claim 1 , wherein

the first wiring board includes a first wiring layer provided on the second principal surface, and the first pad is electrically connected to the first coil via the first wiring layer, and

the second wiring board includes a second wiring layer provided on the fourth principal surface, and the second pad is electrically connected to the second coil via the second wiring layer.

7. The isolator according to claim 6 , wherein

the first wiring layer extends in a first direction,

the second wiring layer extends in the first direction, and

in the first direction, a length of the second wiring board is shorter than a length of the first wiring board.

8. The isolator according to claim 6 , wherein

the first wiring board includes a first via that is provided in the first insulating layer and connects the first coil and the first wiring layer, and a second via that is provided in the first insulating layer and connects the first pad and the first wiring layer, and

the second wiring board includes a third via that is provided in the second insulating layer and connects the second coil and the second wiring layer.

9. The isolator according to claim 6 , wherein

the first wiring board includes a fourth insulating layer and a fifth insulating layer that sandwich the first coil and the first wiring layer, and

the second wiring board includes a sixth insulating layer and a seventh insulating layer that sandwich the second coil and the second wiring layer.

10. The isolator according to claim 6 , wherein

the first coil, the second coil, the first wiring layer, and the second wiring layer include copper.

11. The isolator according to claim 1 , wherein

respective thicknesses of the first coil and the second coil are 6 μm or more and 12 μm or less.

12. The isolator according to claim 1 , wherein

the first coil and the second coil include copper.

13. The isolator according to claim 1 , wherein

the first wiring board and the second wiring board are flexible printed wiring boards.

14. The isolator according to claim 1 , further comprising:

a first semiconductor chip connected to the first pad of the first wiring board via a first wire; and

a second semiconductor chip connected to the second pad of the second wiring board via a second wire.

15. The isolator according to claim 14 , wherein

the first semiconductor chip includes a transmission circuit,

the second semiconductor chip includes a reception circuit,

the first pad is electrically connected to the transmission circuit, and

the second pad is electrically connected to the reception circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2022
From: IMAIZUMI, YUSUKE; LIU, JIA; TAMURA, YOSHINARI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 061021/0224 →
Priority Claims (1)
JP 2022-048518 · Mar 24, 2022 · national
Continuity (1)
Related Publication 20230309228A1 · Sep 28, 2023