IP Library › Granted Patent US 12,192,659
Granted Patent B2
US 12,192,659 · App. 17/904,316 · Granted Jan 7, 2025

Solid-state imaging element, imaging device, and method for controlling solid-state imaging element

Inventor: Luonghung Asakura (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H04N25/771H01L27/14623H04N25/42H04N25/778
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,192,659
App. No.
17/904,316
Granted
Jan 7, 2025
Kind
B2
Abstract

PLS resistance is improved in a solid-state imaging element in which all pixels are simultaneously exposed. A front-stage transfer transistor transfers a charge from a photoelectric conversion element to a front-stage charge holding region and a rear-stage charge holding region which have different capacities. A rear-stage transfer transistor transfers the charge from the rear-stage charge holding region to a floating diffusion region. An intermediate transfer transistor transfers a charge, which remains in the front-stage charge holding region after the charge has been transferred from the rear-stage charge holding region to the floating diffusion region, to the floating diffusion region via the front-stage charge holding region.

Claims (57)

1. A solid-state imaging element, comprising:

a photoelectric conversion element;

a front-stage charge holding region;

a rear-stage charge holding region, wherein a capacity of the rear-stage charge holding region is different from a capacity of the front-stage charge holding region;

a front-stage transfer transistor configured to transfer a first charge from the photoelectric conversion element to the front-stage charge holding region and the rear-stage charge holding region;

a rear-stage transfer transistor configured to transfer the first charge from the rear-stage charge holding region to a floating diffusion region;

an intermediate transfer transistor configured to transfer a second charge, which remains in the front-stage charge holding region after the first charge has been transferred from the rear-stage charge holding region to the floating diffusion region, to the floating diffusion region via the front-stage charge holding region;

a light-shielding wall configured to prevent the first charge to leak from the photoelectric conversion element to the rear-stage charge holding region; and

a signal processing circuit configured to:

compare, between a first pixel signal corresponding to an amount of charge transferred from the rear-stage charge holding region and a second pixel signal corresponding to an amount of charge transferred from the front-stage charge holding region and the rear-stage charge holding region, the first pixel signal with a specific threshold; and

select one of the first pixel signal or the second pixel signal based on a comparison result.

2. The solid-state imaging element according to claim 1 , wherein

the front-stage charge holding region and the rear-stage charge holding region are impurity diffusion regions,

a polarity of the front-stage charge holding region is same as a polarity of the rear-stage charge holding region,

a specific impurity diffusion region is between the front-stage charge holding region and the rear-stage charge holding region, and

a polarity of the specific impurity diffusion region is different from the polarity of the front-stage charge holding region and the rear-stage charge holding region.

3. The solid-state imaging element according to claim 1 , wherein the front-stage charge holding region and the rear-stage charge holding region are in a same impurity diffusion region.

4. The solid-state imaging element according to claim 3 , wherein an impurity concentration in a specific region between the front-stage charge holding region and the rear-stage charge holding region in the same impurity diffusion region is different from an impurity concentration in a vicinity of the specific region.

5. The solid-state imaging element according to claim 3 , further comprising an adjustment transistor configured to adjust a height of a potential barrier between the front-stage charge holding region and the rear-stage charge holding region.

6. The solid-state imaging element according to claim 1 , further comprising a vertical scanning circuit configured to:

control each of the front-stage transfer transistor, the rear-stage transfer transistor, and the intermediate transfer transistor to be turned on or off;

turn the front-stage transfer transistor and the intermediate transfer transistor on while the rear-stage transfer transistor is off to transfer the first charge to the front-stage charge holding region and the rear-stage charge holding region;

turn the rear-stage transfer transistor on while the front-stage transfer transistor and the intermediate transfer transistor are off to transfer the charge from the rear-stage charge holding region to the floating diffusion region; and

turn the intermediate transfer transistor and the rear-stage transfer transistor on to transfer the first charge from the front-stage charge holding region to the floating diffusion region.

7. The solid-state imaging element according to claim 1 , further comprising a specific semiconductor substrate, wherein the photoelectric conversion element is on a wired front surface of both surfaces of the specific semiconductor substrate.

8. The solid-state imaging element according to claim 1 , further comprising a specific semiconductor substrate, wherein the photoelectric conversion element is on a back surface of a wired front surface of both surfaces of the specific semiconductor substrate.

9. The solid-state imaging element according to claim 1 , wherein

the photoelectric conversion element includes a first photoelectric conversion element and a second photoelectric conversion element,

the front-stage charge holding region includes a first front-stage charge holding region and a second front-stage charge holding region,

the rear-stage charge holding region includes a first rear-stage charge holding region and a second rear-stage charge holding region,

the front-stage transfer transistor includes a first front-stage transfer transistor and a second front-stage transfer transistor,

the intermediate transfer transistor includes a first intermediate transfer transistor and a second intermediate transfer transistor, and

the rear-stage transfer transistor includes a first rear-stage transfer transistor and a second rear-stage transfer transistor.

10. The solid-state imaging element according to claim 1 , further comprising:

a charge discharge transistor configured to discharge the first charge from the photoelectric conversion element;

a reset transistor configured to initialize the floating diffusion region;

an amplification transistor configured to amplify a signal corresponding to an amount of charge transferred to the floating diffusion region; and

a selection transistor configured to output the amplified signal as a pixel signal based on a specific selection signal.

11. An imaging device, comprising:

a photoelectric conversion element;

a front-stage charge holding region;

a rear-stage charge holding region, wherein a capacity of the rear-stage charge holding region is different from a capacity of the front-stage charge holding region;

a front-stage transfer transistor configured to transfer a first charge from the photoelectric conversion element to the front-stage charge holding region and the rear-stage charge holding region;

a rear-stage transfer transistor configured to transfer the first charge from the rear-stage charge holding region to a floating diffusion region;

an intermediate transfer transistor configured to transfer a second charge, which remains in the front-stage charge holding region after the first charge has been transferred from the rear-stage charge holding region to the floating diffusion region, to the floating diffusion region via the front-stage charge holding region;

a light-shielding wall configured to prevent the first charge to leak from the photoelectric conversion element to the rear-stage charge holding region; and

a signal processing circuit configured to:

compare, between a first pixel signal corresponding to an amount of charge transferred from the rear-stage charge holding region and a second pixel signal corresponding to an amount of charge transferred from the front-stage charge holding region and the rear-stage charge holding region, the first pixel signal with a specific threshold;

select one of the first pixel signal or the second pixel signal based on a comparison result; and

process the selected one of the first pixel signal or the second pixel signal.

12. A method, comprising:

in a solid-state imaging element comprising:

transferring a first charge from a photoelectric conversion element to a front-stage charge holding region and a rear-stage charge holding region which have different capacities;

transferring the first charge from the rear-stage charge holding region in which leakage of the first charge to the photoelectric conversion element is prevented by a light-shielding wall to a floating diffusion region;

transferring a second charge, which remains in the front-stage charge holding region after the first charge has been transferred from the rear-stage charge holding region to the floating diffusion region, to the floating diffusion region via the front-stage charge holding region;

comparing, between a first pixel signal corresponding to an amount of charge transferred from the rear-stage charge holding region and a second pixel signal corresponding to an amount of charge transferred from the front-stage charge holding region and the rear-stage charge holding region, the first pixel signal with a specific threshold; and

selecting one of the first pixel signal or the second pixel signal based on a comparison result.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 16, 2022
From: ASAKURA, LUONGHUNG
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 060817/0949 →
Priority Claims (1)
JP 2020-030577 · Feb 26, 2020 · national
Continuity (1)
Related Publication 20230053574A1 · Feb 23, 2023
References Cited (6)
US 20170244921A1 · Velichko · 2017 [cited by examiner]
JP 2017076899A · 2017 [cited by applicant]
JP 2018147975A · 2018 [cited by applicant]
JP 2018160485A · 2018 [cited by applicant]
JP 2019169668A · 2019 [cited by applicant]
International Search Report and Written Opinion of PCT Application No. PCT/JP2020/043731, issued on Feb. 16, 2021, 11 pages of ISRWO. [cited by applicant]
Cited By (1)
US 12,727,265