Comparator and analog to digital converter
To prevent occurrence of an input voltage dependent error due to an input parasitic capacitance. A comparator includes: a first transistor and a second transistor that include two sources connected to each other, two gates to which a differential input signal pair are input, and two drains that output a differential output signal pair corresponding to a difference signal of the differential input signal pair; a third transistor that is connected between both the sources of the first transistor and the second transistor and a first reference voltage node, the third transistor being switched on or off in accordance with logic of a first signal; and a fourth transistor that is connected between both the sources of the first transistor and the second transistor and a second reference voltage node, the fourth transistor being switched on or off in accordance with logic of a second signal having logic different from the logic of the first signal.
1. A comparator, comprising:
a first transistor that comprises a first source, a first gate, and a first drain;
a second transistor that comprises a second source, a second gate, and a second drain, wherein
the first source is connected to the second source,
the first gate is configured to receive a first differential input signal pair,
the second gate is configured to receive the first differential input signal pair,
the first drain is configured to output a differential output signal pair,
the second drain is configured to output the differential output signal pair,
the differential output signal pair corresponds to a first difference signal, and
the first difference signal is associated with the first differential input signal pair;
a third transistor that is connected between the first source, the second source, and a first reference voltage node, wherein the third transistor is switched on or switched off based on a first logic of a first signal; and
a fourth transistor connected between the first source, the second source, and a second reference voltage node, wherein
the fourth transistor is switched on or switched off based on a second logic of a second signal, and
the second logic is different from the first logic.
2. The comparator according to claim 1 , wherein
the fourth transistor is switched on in a period in which the first transistor and the second transistor do not perform a comparison operation, and
the comparison operation is associated with the first difference signal.
3. The comparator according to claim 1 , wherein the third transistor is intermittently switched on during a period in which the fourth transistor is switched off.
4. The comparator according to claim 1 , further comprising a latch circuit configured to hold the differential output signal pair.
5. The comparator according to claim 4 , further comprising a waveform shaping circuit configured to perform waveform shaping of the differential output signal pair, wherein
a third signal is based on the waveform shaping, and
the latch circuit is configured to receive the third signal.
6. The comparator according to claim 5 , wherein
the waveform shaping circuit includes two inverters,
the two inverters are configured to invert a third logic, and
the third logic is associated with the differential output signal pair.
7. The comparator according to claim 4 , further comprising a fifth transistor configured to control the latch circuit, wherein
the latch circuit is configured to perform a holding operation based on the first logic of the first signal, and
the fifth transistor is intermittently switched on based on the fourth transistor being switched off.
8. The comparator according to claim 1 , wherein a conductivity type of the fourth transistor is different from a conductivity type of the third transistor.
9. The comparator according to claim 1 , wherein
each of the first transistor, the second transistor, and the third transistor includes an N-type MOS transistor, and
the fourth transistor includes a P-type MOS transistor.
10. The comparator according to claim 1 , wherein
each of the first transistor, the second transistor, and the third transistor includes a P-type MOS transistor, and
the fourth transistor includes an N-type MOS transistor.
11. The comparator according to claim 1 , further comprising:
a first input terminal configured to receive the first differential input signal pair;
a second input terminal configured to receive the first differential input signal pair;
a third input terminal configured to receive a second differential input signal pair;
a fourth input terminal configured to receive the second differential input signal pair; and
a comparison circuit configured to output a third signal corresponding to the first difference signal and a second difference signal, wherein
the first input terminal is configured to receive the first difference signal,
the second input terminal is configured to receive the first difference signal,
the second difference signal is associated with the second differential input signal pair,
the third input terminal is configured to receive the second difference signal,
the fourth input terminal is configured to receive the second difference signal,
the comparison circuit includes:
a first comparison device that includes a sixth transistor, a seventh transistor, an eight transistor, and a ninth transistor; and
a second comparison device that includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor,
the sixth transistor, the seventh transistor, the eight transistor, and the ninth transistor have a same circuit configuration as a circuit configuration of the first transistor, the second transistor, the third transistor, and the fourth transistor, and
the tenth transistor, the eleventh transistor, the twelfth transistor, and the thirteenth transistor have the same circuit configuration as the circuit configuration of the first transistor, the second transistor, the third transistor, and the fourth transistor.
12. An analog to digital converter, comprising:
a first sampling switch configured to sample a first signal associated with a first differential input signal pair;
a first digital to analog converter configured to:
convert the first signal sampled into a first digital signal; and
output a first output signal, wherein
the first output signal has a first voltage level corresponding to a first unconverted bit, and
the first digital signal includes a first plurality of bits in a bit by bit order;
a second sampling switch configured to sample a second signal of the first differential input signal pair;
a second digital to analog converter configured to:
convert the second signal sampled into a second digital signal; and
output a second output signal, wherein
the second output signal has a second voltage level corresponding to a second unconverted bit, and
the second digital signal includes a second plurality of bits in the bit by bit order;
a comparator configured to output a third signal corresponding to a first difference signal, wherein
the first difference signal is associated with the first differential input signal pair, and
the first output signal and the second output signal form a pair; and
a control circuit configured to control the first digital to analog converter and the second digital to analog converter based on a third output signal of the comparator,
wherein the comparator includes:
a first transistor that comprises a first source, a first gate, and a first drain;
a second transistor that comprises a second source, a second gate, and a second drain, wherein
the first source is connected to the second source,
the first gate is configured to receive the first differential input signal pair,
the second gate is configured to receive the first differential input signal pair,
the first drain is configured to output a differential output signal pair,
the second drain is configured to output the differential output signal pair,
the differential output signal pair corresponds to the first difference signal, and
the first difference signal is associated with the first differential input signal pair;
a third transistor that is connected between the first source, the second source, and a first reference voltage node, wherein the third transistor is switched on or switched off based on a first logic of the first signal; and
a fourth transistor that is connected between the first source, the second source, and a second reference voltage node, wherein
the fourth transistor is switched on or switched off based on a second logic of a second signal, and
the second logic is different from the first logic.
13. The analog to digital converter according to claim 12 , further comprising a filter circuit configured to:
sample the first output signal and the second output signal; and
output the first output signal, the second output signal, and a second differential input signal pair, wherein
the comparator is further configured to output a third signal corresponding to the first difference signal and a second difference signal,
the second difference signal corresponds to the second differential input signal pair,
the comparator further includes:
a first input terminal configured to receive the first differential input signal pair;
a second input terminal configured to receive the first differential input signal pair;
a third input terminal configured to receive the second differential input signal pair;
a fourth input terminal configured to receive the second differential input signal pair; and
a comparison circuit configured to output a fourth signal corresponding to the first difference signal and the second difference signal,
the first input terminal is configured to receive the first difference signal,
the second input terminal is configured to receive the first difference signal,
the third input terminal is configured to receive the second difference signal,
the fourth input terminal is configured to receive the second difference signal, and
the comparison circuit includes the first transistor, the second transistor, the third transistor, and the fourth transistor.