IP Library › Granted Patent US 12,471,116
Granted Patent B2
US 12,471,116 · App. 17/914,695 · Granted Nov 11, 2025

Method and apparatus for resource allocation for sidelink communication

Inventors: Haipeng Lei (Haidian District, CN); Xiaodong Yu (Haidian District, CN); Zhennian Sun (Chaoyang District, CN); Haiming Wang (Xicheng District, CN)
Assignee: Lenovo (Beijing) Limited
H04W72/25H04W72/1263H04W76/20
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Quick Facts
Patent No.
US 12,471,116
App. No.
17/914,695
Granted
Nov 11, 2025
Kind
B2
Abstract

The present disclosure is related to methods and apparatuses. According to some embodiments of the disclosure, a method includes: receiving sidelink control information (SCI) on a first interlace of a first set of interlaces on a carrier, wherein the SCI may schedule a second set of interlaces on the carrier for transmitting data; and receiving, based on the SCI, the data on the second set of interlaces, wherein each interlace of the first set of interlaces and the second set of interlaces may include evenly-spaced resource blocks (RBs) in frequency domain.

Claims (37)

1 . A method, comprising:

receiving sidelink control information (SCI) on a first interlace of a first set of interlaces on a carrier, wherein the SCI schedules a second set of interlaces on the carrier for transmitting data based on an interlace mapping between the first set of interlaces and the second set of interlaces, the SCI includes a field indicating a number of interlaces in the first set and the second set of interlaces for data transmission, and a number of bits for the field is dependent on a number of maximum linkages per SCI interlace in the interlace mapping; and

receiving, based on the SCI, the data on the second set of interlaces,

wherein each interlace of the first set of interlaces and the second set of interlaces comprises evenly-spaced resource blocks (RBs) in frequency domain.

2 . The method of claim 1 , wherein one or more of: the first set of interlaces is configured by radio resource control (RRC) signaling, or predefined from a plurality of interlaces specified based on subcarrier spacing of the carrier, or the first set of interlaces includes all interlaces of the plurality of interlaces.

3 . An apparatus, comprising:

a receiving circuitry; and

a processor connected to the receiving circuitry, the processor and the receiving circuitry configured to cause the apparatus to:

receive sidelink control information (SCI) on a first interlace of a first set of interlaces on a carrier, wherein the SCI schedules a second set of interlaces on the carrier for transmitting data based on an interlace mapping between the first set of interlaces and the second set of interlaces, the SCI includes a field indicating a number of interlaces in the first set and the second set of interlaces for data transmission, and a number of bits for the field is dependent on a number of maximum linkages per SCI interlace in the interlace mapping; and

receive, based on the SCI, the data on the second set of interlaces,

wherein each interlace of the first set of interlaces and the second set of interlaces comprises evenly-spaced resource blocks (RBs) in frequency domain.

4 . The apparatus of claim 3 , wherein one or more of: the first set of interlaces is configured by radio resource control (RRC) signaling or predefined from a plurality of interlaces specified based on subcarrier spacing of the carrier, or the first set of interlaces includes all interlaces of the plurality of interlaces.

5 . The apparatus of claim 4 , wherein the RRC signaling indicates one or more of a corresponding index of each interlace in the first set of interlaces, or a number of interlaces in the first set of interlaces.

6 . The apparatus of claim 4 , wherein the first set of interlaces is predefined in a form of one or more of a corresponding index of each interlace in the first set of interlaces, or a number of interlaces in the first set of interlaces.

7 . The apparatus of claim 3 , wherein the SCI is received on a single interlace, and the SCI indicates one or more of a number of interlaces in the second set of interlaces or an interlace pattern index.

8 . The apparatus of claim 7 , wherein the processor is configured to cause the apparatus to determine the second set of interlaces based on the SCI and a mapping between the first set of interlaces and the second set of interlaces.

9 . The apparatus of claim 8 , wherein the mapping is one or more of configured by radio resource control (RRC) signaling or predefined.

10 . The apparatus of claim 3 , wherein the SCI indicates a number of one or more contiguous interlaces, and an index of a starting interlace of the one or more contiguous interlaces.

11 . The apparatus of claim 3 , wherein the SCI indicates a number of one or more contiguous interlaces, and wherein:

a starting interlace of the one or more contiguous interlaces is an interlace next to the first interlace in an ascending order of interlace index, or the starting interlace of the one or more contiguous interlaces is the first interlace; and

the second set of interlaces includes the one or more contiguous interlaces.

12 . An apparatus, comprising:

a receiving circuitry; and

a processor connected to the receiving circuitry, the processor and the receiving circuitry configured to cause the apparatus to:

transmit sidelink control information (SCI) on a first interlace of a first set of interlaces on a carrier, wherein the SCI schedules a second set of interlaces on the carrier for transmitting data based on an interlace mapping between the first set of interlaces and the second set of interlaces, the SCI includes a field indicating a number of interlaces in the first set and the second set of interlaces for data transmission, and a number of bits for the field is dependent on a number of maximum linkages per SCI interlace in the interlace mapping; and

transmit the data on the second set of interlaces according to the SCI;

wherein each interlace of the first set of interlaces and the second set of interlaces comprises evenly-spaced resource blocks (RBs) in frequency domain.

13 . The apparatus of claim 12 , wherein one or more of: the first set of interlaces is configured by radio resource control (RRC) signaling or predefined from a plurality of interlaces specified based on subcarrier spacing of the carrier, or the first set of interlaces includes all interlaces of the plurality of interlaces.

14 . The apparatus of claim 13 , wherein the RRC signaling indicates one or more of a corresponding index of each interlace in the first set of interlaces, or a number of interlaces in the first set of interlaces.

15 . The apparatus of claim 13 , wherein the first set of interlaces is predefined in a form of one or more of a corresponding index of each interlace in the first set of interlaces or a number of interlaces in the first set of interlaces.

16 . The apparatus of claim 12 , wherein the SCI is transmitted on a single interlace, and the SCI indicates one or more of a number of interlaces in the second set of interlaces or an interlace pattern index.

17 . The apparatus of claim 16 , wherein the second set of interlaces is based on the SCI and a mapping between the first set of interlaces and the second set of interlaces.

18 . The apparatus of claim 17 , wherein the mapping is configured by one or more of radio resource control (RRC) signaling or predefined.

19 . The apparatus of claim 12 , wherein the SCI indicates a number of one or more contiguous interlaces, and an index of a starting interlace of the one or more contiguous interlaces.

20 . The apparatus of claim 12 , wherein the SCI indicates a number of one or more contiguous interlaces, and wherein:

a starting interlace of the one or more contiguous interlaces is an interlace next to the first interlace in an ascending order of interlace index, or the starting interlace of the one or more contiguous interlaces is the first interlace; and

the second set of interlaces includes the one or more contiguous interlaces.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2022
From: LEI, HAIPENG; YU, XIAODONG; SUN, ZHENNIAN; WANG, HAIMING
To: LENOVO (BEIJING) LIMITED
Reel/Frame 061218/0458 →
Continuity (1)
Related Publication 20230379939A1 · Nov 23, 2023
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