IP Library › Granted Patent US 12,230,186
Granted Patent B2
US 12,230,186 · App. 17/916,347 · Granted Feb 18, 2025

Pixel driving circuit capable of operating in low-definition mode and high-definition mode using same pixel memory, and display device comprising same

Inventors: Jae Hoon Lee (Busan, KR); Jin Woong Jang (Suwon-si, KR)
Assignee: SAPIEN Semiconductors Inc.
G09G3/32G06F1/163G02B27/017G02B2027/0178G09G2300/0857G09G2310/0272G09G2310/08G09G2330/021G09G2340/04
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,230,186
App. No.
17/916,347
Granted
Feb 18, 2025
Kind
B2
Abstract

Provided is a pixel driving circuit operatable in a low-definition mode and a high-definition mode using the same pixel memory, and a display device including the same. The pixel driving circuit may include a driving line configured to connect between an emitter and a positive power source or between the emitter and a negative power source, a first transistor connected in series on the driving line and turned on in response to a pulse width modulation (PWM) signal, a first driving unit and a second driving unit that are connected in series on the driving line and electrically connected in parallel to each other, and a second transistor connected between a reference voltage source, which is connected to apply a reference voltage to the first driving unit and the second driving unit, and the second driving unit and turned on or off in response to a display mode selection signal.

Claims (29)

1. A pixel driving circuit comprising:

a driving line configured to connect between an output of a first transistor and a positive power source or between the output of the first transistor and a negative power source;

the first transistor connected in series on the driving line and turned on in response to a pulse width modulation (PWM) signal;

a first driving unit and a second driving unit that are connected in series from the driving line to a light emitting diode and electrically connected in parallel to each other; and

a second transistor connected between a reference voltage source and the second driving unit, wherein the reference voltage source is configured to apply a reference voltage to the first driving unit and the second driving unit,

wherein when operating in a first display mode, the first and second driving unit are turned on, and

when operating in a second display mode, the first driving unit is turned on for a cyclic period comprising first and second portion periods, and the second transistor is configured to turn on the second driving unit for the first portion period and turn off the second driving unit for the second portion period,

wherein the second display mode has a higher resolution than the first display mode,

wherein

the first driving unit includes:

a third transistor connected in series on the driving line and turned on in response to the positive power source; and

a fourth transistor connected in series on the driving line and turned on in response to the reference voltage, and

the second driving unit includes:

a fifth transistor connected in series on the driving line and turned on in response to the positive power source; and

a sixth transistor connected in series on the driving line and turned on in response to the reference voltage when the second transistor is turned on.

2. The pixel driving circuit of claim 1 , wherein the second transistor is connected between the reference voltage source and the sixth transistor.

3. The pixel driving circuit of claim 1 , further comprising a seventh transistor connected between the positive power source and the sixth transistor, wherein the seventh transistor is turned on or off in response to a display mode selection signal.

4. The pixel driving circuit of claim 3 , wherein

the first, fourth, sixth, and seventh transistors are P-type metal-oxide silicon field effect transistors (MOSFETs), and

the second, third, and fifth transistors are N-type MOSFETs.

5. A pixel circuit comprising:

the pixel driving circuit of claim 1 ;

an emitter;

a pixel memory configured to store data related to driving of the emitter; and

a pulse width modulation (PWM) controller configured to process a signal for controlling luminance of the emitter.

6. The pixel circuit of claim 5 , wherein the pixel memory includes five static random-access memory (SRAM) cells for storing 5 bits of data related to the driving of the emitter.

7. The pixel driving circuit of claim 1 , wherein

the first display mode is a standard-definition mode, and

the second display mode is a high-definition mode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2022
From: JANG, JIN WOONG
To: SAPIEN SEMICONDUCTORS INC.
Reel/Frame 061275/0234 →
Priority Claims (1)
KR 10-2020-0040501 · Apr 2, 2020 · national
Continuity (1)
Related Publication 20230154387A1 · May 18, 2023
References Cited (15)
US 7336251B2 · Osada · 2008 [cited by examiner]
US 8659521B2 · Osame · 2014 [cited by examiner]
US 20040263440A1 · Kimura · 2004 [cited by examiner]
US 20070080905A1 · Takahara · 2007 [cited by examiner]
US 20170200415A1 · Noguchi · 2017 [cited by examiner]
US 20210056902A1 · Tanaka · 2021 [cited by examiner]
US 20220392402A1 · Ueda · 2022 [cited by examiner]
JP 2011232764A · 2011 [cited by applicant]
KR 1020080052406A · 2008 [cited by applicant]
KR 1020080070045A · 2008 [cited by applicant]
KR 1020150101505A · 2015 [cited by applicant]
KR 1020170079408A · 2017 [cited by applicant]
KR 1020170111788A · 2017 [cited by applicant]
KR 102156270B1 · 2020 [cited by applicant]
International Search Report for PCT/KR2020/014482, dated Jan. 26, 2021. [cited by applicant]