Scramble and descramble hardware implementation method based on data bit width expansion
A scramble and descramble hardware implementation method based on data bit width expansion. After expansion, redundant terms are eliminated, and scramble/descramble operation results within the current operation cycle and the value of the shift register after shifting are calculated at once. The present method exhibits advantageous effects with respect to the scramble and descramble polynomial defined by USB3.1 and PCI-Express3.0 protocols, and can obtain a relatively small hardware delay, so that the system can work at a higher frequency.
1 . A scramble and descramble hardware implementation method based on data bit width expansion, assuming that the data bit width is N, the method comprising the steps of:
performing XOR using a least significant digit of input data with a top bit of a shift register to obtain a least significant digit of an output data;
performing iterations and expansions on the shift register according to a polynomial X23+X21+X16+X8+X5+X2+1 until obtaining a value of the linear feedback shift register after 1 to N iterations, and then eliminating redundant terms in the expansions according to a^a^b=b (a and b are binary variables), wherein single-step algorithm is: D0(n+1)=D22(n); D1(n+1)=D0(n); D2(n+1)=D1(n)^D22(n); D3(n+1)=D2(n); D4(n+1)=D3(n); D5(n+1)=D4(n)^D22(n); D6(n+1)=D5(n); D7(n+1)=D6(n); D8(n+1)=D7(n)^D22(n); D9(n+1)=D8(n); D10(n+1)=D9(n); D11(n+1)=D10(n); D12(n+1)=D11(n); D13(n+1)=D12(n); D14(n+1)=D13(n); D15(n+1)=D14(n); D16(n+1)=D15(n)^D22(n); D17(n+1)=D16(n); D18(n+1)=D17(n); D19(n+1)=D18(n); D20(n+1)=D19(n); D21(n+1)=D20^D22(n); D22(n+1)=D21(n);
wherein symbol “^” represents single-bit data XOR, n represents a value of the shift register of the current cycle, and n+1 represents a value of the shift register after the iterations are completed; and
performing XOR using a respective 1 st bit to (N-1) th bit of the input data with a respective top digit of the shift register that have been iterated respectively for 1 to N-1 times and that the redundant terms have been eliminated respectively, and obtaining 1 th bit to (N-1) th bit of the output data.
2 . The scramble and descramble hardware implementation method based on data bit width expansion according to claim 1 , wherein the shift register is a linear feedback shift register.
3 . The scramble and descramble hardware implementation method based on data bit width expansion according to claim 1 , wherein the data bit width N can be any positive integer.
4 . The scramble and descramble hardware implementation method based on data bit width expansion according to claim 1 , wherein the method is applicable to all USB protocols in which scramble and descramble polynomial is G(X)=X23+X21+X16+X8+X5+X2+1.