Nonvolatile memory

1. A memory device comprising:

a first set of memory cells each of which has a gate connected to a word line, and each of which is configured to store data in a non-volatile manner corresponding to a threshold voltage thereof, the first set of memory cells including a second set of memory cells and a third set of memory cells different from the second set of memory cells;

a temperature sensor;

an interface configured to receive write data; and

control circuitry configured to execute a first programming operation and execute a second programming operation after the first programming operation,

the first programming operation including

by applying a programming voltage to the word line,

setting the threshold voltage of each of the second set of memory cells in a second section corresponding to the write data among a plurality of first sections, and

setting the threshold voltage of each of the third set of memory cells in a third section among the plurality of first sections, and

the second programming operation including

by applying a programming voltage to the word line,

setting the threshold voltage of each of the second set of memory cells in a fifth section corresponding to the write data among a plurality of fourth sections, a total voltage range of the plurality of fourth sections being wider in voltage range than a total voltage range of the plurality of first sections, and

setting the threshold voltage of each of the third set of memory cells in a sixth section or a seventh section among the plurality of fourth sections in accordance with first temperature information detected by the temperature sensor, the sixth section including the same voltage range as the third section, the seventh section being higher in voltage range than the third section.

2. The memory device according to claim 1 , wherein

the control circuitry is further configured to acquire the first temperature information from the temperature sensor in the second programming operation.

3. The memory device according to claim 1 , wherein

the control circuitry is further configured to:

acquire, in the first programming operation, second temperature information from the temperature sensor to select a third section from the plurality of first sections, corresponding to the second temperature information, and

acquire the first temperature information from the temperature sensor in the second programming operation.

4. The memory device according to claim 1 , wherein

the third section is second or higher from a section having the lowest voltage.

5. The memory device according to claim 2 ,

wherein the third section is second or higher from a section having the lowest voltage.

6. The memory device according to claim 3 , wherein

the third section is second or higher from a section having the lower voltage.

7. The memory device according to claim 1 , wherein

the sixth section and the seventh section are apart from each other by two or more of the plurality of fourth sections.

8. The memory device according to claim 2 , wherein

the sixth section and the seventh section are apart from each other by two or more of the plurality of fourth sections.

9. The memory device according to claim 3 , wherein

the sixth section and the seventh section are apart from each other by two or more of the plurality of fourth sections.

10. The memory device according to claim 4 , wherein

the sixth section and the seventh section are apart from each other by two or more of the plurality of fourth sections.

11. The memory device according to claim 5 , wherein

the sixth section and the seventh section are apart from each other by two or more of the plurality of fourth sections.

12. The memory device according to claim 6 , wherein

the sixth section and the seventh section are apart from each other by two or more of the plurality of fourth sections.

13. A memory device comprising:

a first set of memory cells each of which has a gate connected to a word line; and each of which is configured to store data in a non-volatile manner corresponding to a threshold voltage thereof, the first set of memory cells including a second set of memory cells and a third set of memory cells different from the second set of memory cells;

a temperature sensor;

an interface configured to:

receive first write data of P bits per memory cell where P is an integer of one or more, and

receive, after the first write data, second write data of Q bits per memory cell where Q is an integer of one or more; and

control circuitry configured to execute a first programming operation in response to a receipt of the first write data by the interface and execute a second programming operation in response to a receipt of the second write data by the interface,

the first programming operation including

acquiring first temperature information from the temperature sensor, and

by applying a programming voltage to the word line,

setting the threshold voltage of each of the second set of memory cells in a second section corresponding to the first write data among 2 P first sections, and

setting threshold voltage of each of the third set of memory cells in a third section corresponding to the first temperature information, among the 2 P first sections, and

the second programming operation including

acquiring second temperature information from the temperature sensor,

reading the first write data and the first temperature information from the first set of memory cells, and

by applying a programming voltage to the word line,

setting the threshold voltage of each of the second set of memory cells in a fifth section among 2 (P+Q) fourth sections, the second section corresponding to a combination of the first write data and the second write data, and

setting the threshold voltage of each of the third set of memory cells in a sixth section among the 2 (P+Q) fourth sections, the second section corresponding to a combination of the first temperature information and the second temperature information.

14. A memory device comprising:

a first set of memory cells each of which has a gate connected to a word line and each of which is configured to store data in a non-volatile manner corresponding to a threshold voltage thereof, the first set of memory cells including a second set of memory cells, a third set of memory cells different from the second set of memory cells, and a fourth set memory cells different from the second set of memory cells and the third set of memory cells;

a temperature sensor;

an interface configured to receive write data; and

control circuitry configured to execute a first programing operation and execute a second programming operation after the first programming operation,

the first programming operation including

acquiring first temperature information from the temperature sensor, and

by applying a programming voltage to the word line,

setting the threshold voltage of each of the second set of memory cells in a second section corresponding to the write data among a plurality of first sections,

setting the threshold voltage of each of the third set of memory cells in a third section among the plurality of first sections, the third section corresponding to the first temperature information, and

setting the threshold voltage of each of the fourth set of memory cells in a fourth section among the plurality of first sections, the fourth section corresponding to the first temperature information, and

the second programming operation including

acquiring second temperature information from the temperature sensor,

by applying a programming voltage to the word line,

setting the threshold voltage of each of the second set of memory cells in a sixth section corresponding to the write data among a plurality of fifth sections, a total voltage range of the plurality of fifth sections being wider in voltage range than a total voltage range of the plurality of first sections, and

setting the threshold voltage of each of the fourth set of memory cells in a seventh section or an eighth section in accordance with the second temperature information among the plurality of fifth sections, the seventh section including the same voltage range as the fourth section, the eighth section being higher in voltage range than the fourth section.

15. The memory device according to claim 14 , wherein

the fourth section is second or higher from a section having the lowest voltage.

16. The memory device according to claim 14 , wherein

the seventh section and the eighth section are apart from each other by two or more of the plurality of fifth sections.

17. The memory device according to claim 15 , wherein

the seventh section and the eighth section are apart from each other by two or more of the plurality of fifth sections.