Semiconductor structure

1. A semiconductor structure, comprising:

a substrate comprising a well region, a first conductivity type doped region in the well region, and a second conductivity type doped region in the well region, wherein the second conductivity type doped region surrounds the first conductivity type doped region and comprises a first portion and a second portion perpendicular to the first portion in a top view;

an anti-fuse disposed in an anti-fuse region of the first conductivity type doped region;

a first transistor and a second transistor disposed in the well region, wherein the anti-fuse is disposed between the first transistor and the second transistor, and the anti-fuse is electrically connected to the first transistor and the second transistor;

a contact structure disposed above the anti-fuse; and

a dielectric layer disposed between the contact structure and the anti-fuse region of the first conductivity type doped region.

2. The semiconductor structure of claim 1 , wherein the second conductivity type doped region further comprises a third portion parallel to the first portion in the top view.

3. The semiconductor structure of claim 2 , wherein the second conductivity type doped region further comprises a fourth portion perpendicular to the third portion in the top view.

4. The semiconductor structure of claim 3 , wherein the first portion, the second portion, the third portion, and the fourth portion of the second conductivity type doped region form a ring profile in the top view.

5. The semiconductor structure of claim 1 , wherein a lengthwise direction of the contact structure is perpendicular to that of the second portion of the second conductivity type doped region in the top view.

6. The semiconductor structure of claim 1 , further comprising:

a first contact and a second contact disposed above the anti-fuse region, wherein the first contact and the second contact are disposed on opposite sides of the contact structure.

7. The semiconductor structure of claim 1 , further comprising:

a third contact disposed above a source/drain region of the first transistor; and

a fourth contact disposed above a source/drain region of the second transistor.

8. The semiconductor structure of claim 1 , further comprising:

a first conductive structure disposed above the first transistor and the anti-fuse such that the anti-fuse is electrically connected to the first transistor; and

a second conductive structure disposed above the second transistor and the anti-fuse such that the anti-fuse is electrically connected to the second transistor.

9. The semiconductor structure of claim 1 , wherein the first transistor and the second transistor are connected in parallel and share a gate structure.

10. The semiconductor structure of claim 9 , wherein a top surface of the contact structure is substantially coplanar with a top surface of the gate structure of the first transistor.

11. A semiconductor structure, comprising:

a substrate comprising a well region, a first conductivity type doped region in the well region, and a second conductivity type doped region in the well region, wherein the second conductivity type doped region surrounds the first conductivity type doped region and comprises a first portion and a second portion perpendicular to the first portion in a top view;

an isolation structure disposed in the substrate and configured to electrically insulate the first conductivity type doped region from the second conductivity type doped region;

an anti-fuse disposed in an anti-fuse region of the first conductivity type doped region;

a first transistor and a second transistor disposed in the well region, wherein the anti-fuse is disposed between the first transistor and the second transistor, and the anti-fuse is electrically connected to the first transistor and the second transistor; and

a contact structure disposed above the anti-fuse.

12. The semiconductor structure of claim 11 , wherein the first transistor and the second transistor are connected in parallel and share a first gate structure.

13. The semiconductor structure of claim 12 , further comprising:

a third transistor and a fourth transistor, wherein the second transistor is closer to the third transistor than the first transistor, and the third transistor and the fourth transistor are connected in parallel and share a second gate structure.

14. The semiconductor structure of claim 13 , wherein a minimum distance between the first gate structure and the second gate structure is in a range of about 40 nanometers to about 200 nanometers.

15. The semiconductor structure of claim 13 , further comprising:

a conductive structure disposed above the second transistor and the third transistor such that the second transistor is electrically connected to the third transistor.

16. The semiconductor structure of claim 11 , wherein the well region has a conductivity type the same as that of the second conductivity type doped region and different from that of the first conductivity type doped region.

17. The semiconductor structure of claim 11 , wherein the first portion of the second conductivity type doped region has a strip profile in the top view.

18. The semiconductor structure of claim 11 , wherein the second portion of the second conductivity type doped region has a shape substantially the same as that of the first portion of the second conductivity type doped region in the top view.

19. The semiconductor structure of claim 11 , wherein the second conductivity type doped region further comprises:

a third portion parallel to the first portion in the top view; and

a fourth portion perpendicular to the third portion in the top view.

20. The semiconductor structure of claim 19 , wherein the first portion, the second portion, the third portion, and the fourth portion of the second conductivity type doped region form a ring profile in the top view.