Hardware-efficient PAM-3 encoder and decoder
Data bits are encoded in one or both of an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol (11b7s) format and a three bit two symbol (3b2s) format on a plurality of data channels, one or more auxiliary data channels, and an error correction channel. One or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as 11b7s and/or 3b2s PAM-3 symbols on an error correction channel.
1. A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits, the transceiver comprising:
a plurality of communication channels comprising a plurality of data channels, a plurality of auxiliary data channels, and an error correction channel;
an encoder configured to:
apply 11b7s encoding to at least some of the data bits to generate first PAM-3 symbols on each of the plurality of communication channels; and
apply 11b7s encoding to a combination of 3 of the data bits and 8 bits of a cyclic redundancy check (CRC) value comprised by the meta-data bits to generate a first set of 7 PAM-3 symbols on the error correction channel.
2. The transceiver of claim 1 , wherein the plurality of communication channels consist of eight data channels, two auxiliary data channels, and the error correction channel.
3. The transceiver of claim 1 , wherein the burst of data bits consists of 256 data bits.
4. The transceiver of claim 1 , wherein the meta-data bits consist of the CRC value and one or both of a poison bit and a severity bit, and the encoder is further configured to apply 11b7s encoding to the meta-data bits to generate second PAM-3 symbols on the error correction channel.
5. The transceiver of claim 1 , the encoder further configured to apply 11b7s encoding to a combination of 10 bits of the CRC value and either a poison bit or a severity bit to generate a second set of 7 PAM-3 symbols on the error correction channel.
6. A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits, the transceiver comprising:
a plurality of communication channels comprising a plurality of data channels, a plurality of auxiliary data channels, and an error correction channel;
a decoder configured to:
apply 11b7s decoding to recover at least some of the data bits from first PAM-3 symbols on each of the plurality of communication channels; and
apply 11b7s decoding to a first set of 7 PAM-3 symbols on the error correction channel to recover 3 of the data bits and 8 bits of a cyclic redundancy check (CRC) value.
7. The transceiver of claim 6 , wherein the plurality of communication channels consist of eight data channels, two auxiliary data channels, and the error correction channel.
8. The transceiver of claim 6 , wherein the burst of data bits consists of 256 data bits.
9. The transceiver of claim 6 , wherein the meta-data bits consist of the CRC value and one or both of a poison bit and a severity bit, and the decoder is further configured to apply 11b7s decoding to the meta-data bits to recover one or both of the poison bit and the severity bit on the error correction channel.
10. The transceiver of claim 6 , the decoder further configured to apply 11b7s decoding to a second set of 7 PAM-3 symbols on the error correction channel to recover 10 bits of the CRC value and either a poison bit or a severity bit.
11. A method of communicating data bits and meta-data bits in a device, the method comprising:
communicating the data bits in a burst over a plurality of communication channels comprising a plurality of data channels, a plurality of auxiliary data channels, and an error correction channel;
operating an 11b7s encoder on at least some of the data bits to generate first PAM-3 symbols on each of the data channels, auxiliary data channels, and the error correction channel; and
operating the 11b7s encoder on a combination of 10 bits of a cyclic redundancy check (CRC) of the meta-data bits and either a poison bit or a severity bit of the meta-data bits to generate a first set of 7 PAM-3 symbols on the error correction channel.
12. The method of claim 11 , wherein the plurality of communication channels consist of eight data channels, two auxiliary data channels, and the error correction channel.
13. The method of claim 11 , wherein the burst of data bits consists of 256 data bits.
14. The method of claim 11 , further comprising:
operating the 11b7s encoder on a combination of 3 of the data bits and 8 bits of the CRC to generate a second set of 7 PAM-3 symbols on the error correction channel.
15. A system comprising:
a machine memory;
a data processor;
a memory bus coupling the machine memory to the data processor, the memory bus comprising eight data channels, two auxiliary data channels, and one error correction channel;
an encoder configured to apply 11b7s encoding to a burst of data bits to communicate over the memory bus to generate first PAM-3 symbols on each of eight data channels, two auxiliary data channels, and one error correction channel;
the encoder configured to apply 11b7s encoding to a combination of 3 of the data bits and 8 bits of a cyclic redundancy check (CRC) to generate a first set of 7 PAM-3 symbols on the error correction channel; and
the encoder configured to apply 11b7s encoding to a combination of 10 bits of the CRC and either a poison bit or a severity bit to generate a second set of 7 PAM-3 symbols on the error correction channel.
16. The system of claim 15 , the encoder further configured generate second PAM-3 symbols on the error correction channel by applying 11b7s encoding to meta-data bits for the data bits, the meta-data bits comprising the CRC and one or both of the poison bit and the severity bit.