Dynamic, low-latency, dependency-aware scheduling on SIMD-like devices for processing of recurring and non-recurring executions of time-series data

1. An apparatus for parallel processing, comprising:

a memory; and

one or more processors coupled to the memory, at least one of the one or more processors configured to operate in a single instruction, multiple data (SIMD) model, and the one or more processors configured to:

process a plurality of data samples associated with one or more chains or graphs of data processing operations, the one or more chains or graphs of data processing operations comprising processing steps to be executed repeatedly on first data samples of the plurality of, the first data samples being a subset of temporally ordered samples stored as a pool of sets of the plurality of data samples in the memory, wherein the pool of sets of the plurality of data samples is organized as a hierarchy of queues, each queue in the hierarchy being associated with a different one of the processors, processing priorities of the pluralities of data samples, resource requirements, or processing state of the plurality of data samples, and

dynamically schedule processing of the sets of the plurality of data samples in accordance with the one or more chains or graphs of data processing operations using the hierarchy of queues and according to priority or execution deadlines for the sets of the plurality of data samples and required resources for the processing of the sets of the plurality of data samples, said required resources including one or more of: a number of threads, registers, local shared memory, number of required synchronization barriers, and execution time of processing of the pool of the sets of the plurality data samples by the one or more processors,

wherein the sets of the plurality of data samples are associated with a single one of the one or more chains or graphs of data processing operations or different ones of the one or more chains and graphs of data processing operations, each respective set of the plurality of data samples is of equal or a different number of data samples as others of the sets of the plurality of data samples, and each respective set of the plurality of data samples maps to multiple processing threads executing on the one or more processors configured to operate in the SIMD model and a same or different ones of the processing steps represented by different ones of the data processing operations.

2. The apparatus of claim 1 , wherein each of the one or more processors is connected to a limited amount of resources, which resources include some or all of register files, shared memory, thread state registers, named barriers, and shared caches.

3. The apparatus of claim 1 , wherein the required resources for the processing of the sets of data samples of the pool include one or more of: a number of threads, registers, local shared memory, number of required synchronization barriers, and execution time.

4. The apparatus of claim 1 , wherein the plurality of data samples is associated with a pre-recorded, generated, or live-translated stream of samples forming an audio track.

5. The apparatus of claim 1 , wherein the one or more chains or graphs of data processing operations is associated with one or more clients and each client, graph, or chain is associated with a processing quota or priority, which processing quota or priority is considered for scheduling.

6. The apparatus of claim 1 , wherein the plurality of data samples is received from at least one of: disc; a remote device; a network; another processor; an external workstation; and a digital audio workstation.

7. The apparatus of claim 1 , wherein the sets of the plurality of data samples are associated with respective tasks, the respective tasks use thread counts smaller than a SIMD width of the one or more processors, and multiple ones of the sets of the plurality of data samples for each common task are combined to reach the SIMD width of the one or more processors.

8. The apparatus of claim 1 , wherein information about the graphs and chains of data processing operations is computed upon changes to the graphs or data processing operations and processing of the plurality of data samples is divided into a configuration phase and an execution phase.

9. The apparatus of claim 8 , wherein the changes to the graphs or data processing operations include one or more of: addition or deletion of data processors, input or output connection changes between data processors being altered, changes to a data processor's task being made, and a number of tasks being altered.

10. The apparatus of claim 8 , wherein during the configuration phase, a possible execution of ones of the plurality of data samples and their flow through the graph or chain of data processing operations is split into parallel and sequential processing operations, creating a dependency graph of tasks and data samples, the sets of the plurality of data samples being associated with samples being made available as inputs to the graph or chain of data processing operations or only becoming available after processing of a task associated with one or more of the data processors.

11. The apparatus of claim 1 , wherein the dynamic scheduling includes determining per-chain or per-graph processing blueprints that include information concerning a configuration phase of the dynamic scheduling and information concerning memory locations for data associated with each task of each data processor prior to executing a processing phase of the dynamic scheduling.

12. The apparatus of claim 11 , wherein the processing blueprints include task information, input and output data locations, task and data processor parameters and resource requirements, and task dependency pointers and counters for the processing phase.

13. The apparatus of claim 12 , wherein the one or more chains or graphs of data processing operations are associated with one or multiple threads executing on a secondary processor communicably coupled to the apparatus to allocate memory on the secondary processor and on the apparatus to produce executable descriptions from the processing blueprints and insert incoming ones of the plurality of data samples into the executable descriptions.

14. The apparatus of claim 13 , wherein each of the one or multiple threads associates one or more of the executable descriptions with a processing step of the processing phase.