Integrated circuit with physically unclonable function robust to machine learning attacks
An integrated circuit is provided which includes a physically unclonable function (PUF). The integrated circuit comprises a PUF block including a plurality of physically unclonable function (PUF) cells configured to output a cell signal having a unique value according to an input, a conversion unit is configured to receive the cell signal as input, convert the cell signal, and output a conversion signal. A select signal generator provides a first selection signal to the conversion unit. A key generator is configured to receive the conversion signal from the conversion unit and generate a security key therefrom, wherein the conversion unit includes a first layer which outputs a second signal obtained by converting a provided first signal on the basis of a bit value of the first selection signal.
1. An integrated circuit comprising:
a PUF block including a plurality of physically unclonable function (PUF) cells, each PUF cell being configured to output a cell signal having a unique value according to an input challenge, wherein the cell signals output by the plurality of PUF cells is a first signal;
a select signal generator configured to provide a plurality of selection signals;
a conversion unit configured to receive the plurality of selection signals from the select signal generator and the first signal from the PUF block, convert the first signal into a plurality of conversion signals on the basis of the plurality of selection signals, and output the plurality of conversion signals; and
a key generator configured to receive the plurality of conversion signals from the conversion unit, and generate a security key,
wherein the conversion unit includes a first layer comprises a first and second conversion block receiving a second signal and different selection signal among the plurality of selection signals, respectively, and configured to output a third signal, by converting the second signal, on the basis of the plurality of selection signals from the select signal generator,
wherein the conversion unit further includes a plurality of stages and a plurality of layers, alternately disposed, wherein the plurality of stages each receive a first selection signal of the plurality of selection signals and the plurality of layers each receive a second selection signal of the plurality of selection signals,
wherein the width of the conversion unit is configured to change according to the first selection signal, and
the first signal is converted into a conversion signal of the plurality of conversion signals on the basis of a bit value of the second selection signal defining an internal connection structure of each group of the plurality of groups.
2. The integrated circuit of claim 1 , wherein each layer of the plurality of layers of the conversion unit includes at least two multiplexers (MUX), and
wherein the number of multiplexers included in each layer is the same.
3. The integrated circuit of claim 1 , wherein the bit value of the second selection signal during a first challenge is different from the bit value of the second selection signal during a second challenge.
4. The integrated circuit of claim 1 , wherein the conversion unit further comprises:
a first stage including a plurality of first logical gates of the plurality of logical gates configured to receive a plurality of corresponding inputs of the first signal, perform a logical operation on the first signal and output a second signal;
a second layer configured to receive a second signal, output a third signal by converting the second signal on the basis of a bit value of a second selection signal of the plurality of selection signals; and
a second stage including a plurality of second logical gates, configured to receive the third signal, perform a logical operation on the third signal output a fourth signal.
5. The integrated circuit of claim 4 , wherein the number of the first logical gates included in the first stage is the same as the number of the second logical gates included in the second stage.
6. The integrated circuit of claim 4 ,
wherein the conversion unit deactivates a first logical gate of at least a part of the first stage on the basis of the first selection signal, and
wherein the conversion unit deactivates a second logical gate of at least a part of the second stage on the basis of the first selection signal.
7. The integrated circuit of claim 6 , wherein the number of deactivated first logical gates of the first stage is the same as the number of deactivated second logical gates of the second stage.
8. The integrated circuit of claim 4 , wherein the logical operation is an XOR operation.