Topological insulator-based multiplexer/demultiplexer
An exemplary embodiment of the present disclosure provides a multiplexer/demultiplexer, comprising a plurality of unit cells arranged in a lattice, a first domain, a second domain, a third domain, and a controller. Each of the unit cells can comprise a topological-insulative material, a first piezoelectric patch, and a second piezoelectric patch. A first domain can comprise a first portion of the plurality of unit cells. A second domain can comprise a second portion of the plurality of unit cells. A third domain can comprise a third portion of the plurality of unit cells. The controller can be configured to: apply a negative capacitance to the first piezoelectric patches in the first domain; apply a negative capacitance to the second piezoelectric patches in the second domain; and alternately apply a negative capacitance to the first and second piezoelectric patches, respectively, in the third domain.
1. A multiplexer/demultiplexer comprising:
unit cells arranged in a lattice, each of the unit cells comprising:
a topological-insulative material;
a first piezoelectric patch; and
a second piezoelectric patch;
a first domain comprising a first portion of the unit cells;
a second domain comprising a second portion of the unit cells;
a third domain comprising a third portion of the unit cells; and
a controller configured to:
apply a negative capacitance to the first piezoelectric patches in the first portion of the unit cells;
apply a negative capacitance to the second piezoelectric patches in the second portion of the unit cells; and
alternately apply a negative capacitance to the first and second piezoelectric patches, respectively, in the third portion of the unit cells.
2. The multiplexer/demultiplexer of claim 1 further comprising:
a first acoustic wave port positioned at an interface of the first domain and the second domain proximate a first edge of the lattice, the first acoustic wave port configured to transmit an acoustic wave to and/or receive an acoustic wave from the lattice;
a second acoustic wave port positioned at an interface of the first domain and the third domain proximate a second edge of the lattice, the first second acoustic wave port configured to transmit an acoustic wave to and/or receive an acoustic wave from the lattice; and
a third acoustic wave port positioned at an interface of the second domain and the third domain proximate a third edge of the lattice, the first third acoustic wave port configured to transmit an acoustic wave to and/or receive an acoustic wave from the lattice.
3. The multiplexer/demultiplexer of claim 2 , wherein the multiplexer/demultiplexer is configured such that when a negative capacitance is applied to the:
first piezoelectric patches in the first and third portions of the unit cells; and
the second piezoelectric patches in the second portion of the unit cells;
acoustic waves propagate between the first acoustic wave port and the third acoustic wave port along topological domain walls.
4. The multiplexer/demultiplexer of claim 2 , wherein the multiplexer/demultiplexer is configured such that when a negative capacitance is applied to the:
first piezoelectric patches in the first portion of the unit cells; and
the second piezoelectric patches in the second and third portions of the unit cells;
acoustic waves propagate between the first acoustic wave port and the second acoustic wave port along topological domain walls.
5. The multiplexer/demultiplexer of claim 2 , wherein the first acoustic wave port is an input and the second and third acoustic wave ports are outputs, such that the multiplexer/demultiplexer is configured as a demultiplexer.
6. The multiplexer/demultiplexer of claim 2 , wherein the first acoustic wave port is an output and the second and third acoustic wave ports are inputs, such that the multiplexer/demultiplexer is configured as a multiplexer.
7. The multiplexer/demultiplexer of claim 2 , wherein the interfaces between the first, second, and third domains are separated by an angle of about 120 degrees.
8. The multiplexer/demultiplexer of claim 1 , wherein the controller comprises a negative capacitance circuit comprising:
an operational amplifier;
a first resistor;
a second resistor in series with the first resistor; and
a capacitor.
9. The multiplexer/demultiplexer of claim 1 , wherein the lattice has a hexagonal shape.
10. The multiplexer/demultiplexer of claim 1 , wherein each of the unit cells is configured such that an application of negative capacitance to one of the first and second piezoelectric patches causes a break in inversion symmetry of the respective unit cell.
11. A multiplexer/demultiplexer comprising:
a first domain of unit cells;
a second domain of unit cells;
a third domain of unit cells; and
wherein:
the unit cells of the domains are collectively arranged in a lattice;
each unit cell comprises:
a topological-insulative material;
a first piezoelectric patch; and
a second piezoelectric patch; and
a controller is configured to control the propagation of a wave through the lattice by:
applying a negative capacitance to the first piezoelectric patches in the first domain;
applying a negative capacitance to the second piezoelectric patches in the second domain; and
alternatingly applying a negative capacitance to the first and second piezoelectric patches, respectively, of the third domain.
12. The multiplexer/demultiplexer of claim 11 , wherein the controller comprises a negative capacitance circuit comprising;
an operational amplifier;
a first resistor;
a second resistor in series with the first resistor; and
a capacitor.
13. The multiplexer/demultiplexer of claim 11 further comprising:
a first port positioned at an interface between the first and second domains;
a second port positioned at an interface between the first and third domains; and
a third port positioned at an interface between the second and third domains.
14. The multiplexer/demultiplexer of claim 13 , wherein the multiplexer/demultiplexer is configured such that when a negative capacitance is applied to:
the first piezoelectric patches in the first and third domains; and
the second piezoelectric patches in the second domain;
waves propagate between the first port and the third port along topological domain walls.
15. The multiplexer/demultiplexer of claim 13 , wherein the multiplexer/demultiplexer is configured such that when a negative capacitance is applied to:
the first piezoelectric patches in the first domain; and
the second piezoelectric patches in the second and third domains;
waves propagate between the first port and the second port along topological domain walls.
16. The multiplexer/demultiplexer of claim 13 , wherein the first port is an input and the second and third ports are outputs, such that the multiplexer/demultiplexer is configured as a demultiplexer.
17. The multiplexer/demultiplexer of claim 13 , wherein the first port is an output and the second and third ports are inputs, such that the multiplexer/demultiplexer is configured as a multiplexer.
18. The multiplexer/demultiplexer of claim 13 , wherein:
the lattice has a hexagonal shape; and
the interfaces between the first, second, and third domains are separated by an angle of about 120 degrees.
19. The multiplexer/demultiplexer of claim 11 , wherein each of the unit cells is configured such that an application of negative capacitance to one of the first and second piezoelectric patches causes a break in inversion symmetry of the respective unit cell.