Heater for phase change material memory cell

1. An integrated circuit comprising:

a field effect transistor (FET);

an interconnect connected to a gate of the FET; and

a phase change memory (PCM) cell comprising a phase change section and a first heater, wherein a bottom surface of the first heater is at or below a top surface of the gate, and wherein a top surface of the phase change section is at or below the top surface of the interconnect.

2. The integrated circuit of claim 1 , wherein:

the phase change section further comprises a phase change material; and

a bottom surface of the phase change section is below the top surface of the interconnect.

3. The integrated circuit of claim 2 , wherein:

the PCM cell further comprises a second heater;

a bottom surface of the second heater is at or below a top surface of the gate; and

a top surface of the first heater and a top surface of the second heater are in direct contact with the bottom surface of the phase change section.

4. The integrated circuit of claim 2 , wherein:

the first heater has a first width;

the phase change section has a second width; and

the second width is greater than or equal to twice the first width to form a mushroom-type phase change cell.

5. The integrated circuit of claim 2 , wherein:

the phase change section overlaps the gate; and

a first cap is positioned between the phase change section and the gate.

6. The integrated circuit of claim 1 , wherein:

the FET comprises a substrate; and

the bottom surface of the first heater is in direct contact a source/drain terminal.

7. The integrated circuit of claim 6 , wherein the source/drain terminal is a doped portion of the substrate.

8. The integrated circuit of claim 1 , wherein a width of the bottom surface of the first heater is inset within a width of the source/drain terminal.

9. The integrated circuit of claim 1 , further comprising a second cap on top of the gate.

10. The integrated circuit of claim 1 , wherein the FET has a fin-shaped configuration.

11. A method of manufacturing an integrated circuit, the method comprising:

providing a substrate with a plurality of gates on the substrate and a plurality of trenches therebetween, wherein the trenches are filled with a fill material;

depositing, selectively, a blocking layer over a first group of the plurality of trenches, leaving a second group of the plurality of trenches exposed;

filling the second group with a conductor material;

removing at least some of the blocking layer to expose the first group;

filling the first group with a heater material;

forming phase change section on at least one of the first group, wherein the phase change section comprises a phase change material; and

forming an electrode on the phase change section.

12. The method of claim 11 , further comprising forming a nitride cap over the second group after the filling the second group with the conductor material.

13. The method of claim 12 , further comprising performing chemical mechanical planarization (CMP) after the filling the first group with a heater material to planarize the heater material and the conductor material in the first group and the second group, respectively.

14. The method of claim 11 , wherein the phase change section and the electrode extend over two adjacent trenches in the first group.

15. The method of claim 11 , wherein:

the at least one of the first group has a first width;

the phase change section has a second width; and

the second width is greater than or equal to twice the first width to form a mushroom-type phase change cell.

16. The method of claim 11 , wherein the fill material comprises an oxide material.

17. The method of claim 11 , further comprising forming a via that is electrically connected to the electrode.

18. The method of claim 11 , further comprising removing the fill material from the first group before the filling the first group with the heater material.

19. An integrated circuit comprising:

a substrate; and

a plurality of levels stacked on the substrate, wherein:

a trench silicide (TS) level is a level in direct contact with the substrate;

a contact (CA/CB) level is a level in direct contact with the TS level;

a metal level is a level in direct contact with the CA/CB level; and

a phase change memory (PCM) cell is positioned in the TS and CA/CB levels.