IP Library › Granted Patent US 12,056,377
Granted Patent B2
US 12,056,377 · App. 17/937,068 · Granted Aug 6, 2024

Memory storage device and electronic device including a nonvolatile memory with configurable capacity for providing host data

Inventors: Sun-Mi Yoo (Seoul, KR); Young-Sik Lee (Suwon-si, KR); Jeong-Eun Kim (Seongnam-si, KR); Hye Ju Kim (Seongnam-si, KR); So Dam Hwang (Hwaseong-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F3/064G06F3/0607G06F3/0658G06F3/0679G06F12/0253
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Quick Facts
Patent No.
US 12,056,377
App. No.
17/937,068
Granted
Aug 6, 2024
Kind
B2
Abstract

A memory storage device includes a non-volatile memory including a plurality of memory blocks and a memory controller configured to control the non-volatile memory, wherein the memory controller is configured to provide host data including write data to the non-volatile memory, wherein the memory controller is configured to perform a garbage collection operation on the memory blocks to provide garbage collection data to the non-volatile memory when a free block count of the memory blocks is smaller than a first threshold value, and wherein the memory controller is configured to increase a capacity for providing the host data when the free block count of the memory blocks is greater than a second threshold value less than the first threshold value and a valid page count of the first memory block among the memory blocks is less than a third threshold value.

Claims (42)

1. A memory storage device comprising:

a non-volatile memory including a plurality of memory blocks; and

a memory controller configured to control the non-volatile memory,

wherein the memory controller is configured to provide host data including write data to the non-volatile memory,

wherein the memory controller is configured to perform a garbage collection operation on the memory blocks to provide garbage collection data to the non-volatile memory when a free block count of the memory blocks is less than a first threshold value,

wherein the memory controller is configured to increase a capacity for providing the host data when the free block count of the memory blocks is greater than a second threshold value less than the first threshold value and a valid page count of a first memory block among the memory blocks is less than a third threshold value, and

wherein the memory controller is configured to decrease the capacity for providing the host data when a valid page count of a second memory block different from the first memory block among the memory blocks is equal to or greater than the third threshold value.

2. The memory storage device of claim 1 , wherein the memory controller is configured not to perform the garbage collection operation on the memory blocks and not to provide the garbage collection data to the non-volatile memory when the free block count of the memory blocks is equal to or greater than the first threshold value.

3. The memory storage device of claim 1 , wherein the memory controller is configured to increase a capacity for providing the garbage collection data when the valid page count of the second memory block different from the first memory block among the memory blocks is equal to or greater than the third threshold value.

4. The memory storage device of claim 1 , wherein the memory controller is configured to decrease the capacity for providing the host data when the free block count of the memory blocks is equal to or less than the second threshold value.

5. The memory storage device of claim 1 , wherein the memory controller is configured to decrease a capacity for providing the garbage collection data when the valid page count of the first memory block among the memory blocks is less than the third threshold value.

6. The memory storage device of claim 1 , wherein the memory controller is configured to increase a ratio of the capacity for providing the host data to the capacity for providing the host data and a capacity for providing the garbage collection data.

7. The memory storage device of claim 1 , wherein the memory controller is configured to store meta data that includes information about the write data, and

wherein the meta data is configured to include the valid page count of the first memory block in which the write data is stored and the free block count of the memory blocks.

8. The memory storage device of claim 1 , wherein the non-volatile memory is configured to program the write data in the memory blocks in response to receiving the host data, and is configured to generate a free block in response to receiving the garbage collection data.

9. A memory storage device comprising:

a non-volatile memory including a plurality of memory blocks; and

a memory controller including a memory interface connected to the non-volatile memory,

wherein the memory controller is configured to provide host data including write data to the memory interface,

wherein the memory controller is configured to provide garbage collection data to the memory interface when a free block count of the memory blocks is less than a first threshold value,

wherein the memory interface is configured to provide one or both of the host data and the garbage collection data to the non-volatile memory,

wherein the memory interface is configured not to control a ratio of a capacity for providing the host data to a capacity for providing the garbage collection data when a valid page count of a first memory block among the memory blocks is less than a third threshold value, and

wherein the memory interface is configured to control the ratio of the capacity for providing the host data to the capacity for providing the garbage collection data when the valid page count of the first memory block among the memory blocks is equal to or greater than the third threshold value.

10. The memory storage device of claim 9 , wherein the memory controller is configured to control the ratio of the capacity for providing the host data to the capacity for providing the garbage collection data when the free block count of the memory blocks is equal to or less than a second threshold value less than the first threshold value.

11. The memory storage device of claim 10 , wherein the memory controller is configured to control the ratio of the capacity for providing the host data to the capacity for providing the garbage collection data when the free block count of the memory blocks is greater than the second threshold value, and the valid page count of the first memory block is equal to or greater than the third threshold value.

12. The memory storage device of claim 9 , wherein control of the ratio of the capacity for providing the host data to the capacity for providing the garbage collection data includes control of a decrease of the capacity for providing the host data and control of an increase of the capacity for providing the garbage collection data.

13. The memory storage device of claim 9 , wherein the memory controller is configured to increase the capacity for providing the host data and decrease the capacity for providing the garbage collection data when the ratio of the capacity for providing the host data to the capacity for providing the garbage collection data is not controlled.

14. The memory storage device of claim 9 , wherein a processing capacity of the memory interface corresponds to a sum of the capacity for providing the host data and the capacity for providing the garbage collection data.

15. The memory storage device of claim 9 , wherein the memory controller is configured to store meta data that includes information about the write data, and

wherein the meta data is configured to include a valid page count of the memory block in which the write data is stored and the free block count of the memory blocks.

16. The memory storage device of claim 9 , wherein the non-volatile memory is configured to program the write data in the memory blocks in response to receiving the host data, and is configured to generate a free block in response to the garbage collection data.

17. An electronic device comprising:

a non-volatile memory including a plurality of memory blocks;

a memory controller configured to control the non-volatile memory; and

a host connected to the memory controller,

wherein the host is configured to provide host data to the non-volatile memory,

wherein the memory controller is configured to perform a garbage collection operation on the memory blocks to provide garbage collection data to the non-volatile memory when a free block count of the memory blocks is less than a first threshold value,

wherein the memory controller is configured to increase a capacity for providing the host data, and is configured to decrease a capacity for providing the garbage collection data when the free block count of the memory blocks is greater than a second threshold value less than the first threshold value, and a valid page count of a first memory block among the memory blocks is less than a third threshold value, and

wherein the memory controller is configured to decrease the capacity for providing the host data and is configured to increase the capacity for providing the garbage collection data when a valid page count of a second memory block different from the first memory block among the memory blocks is equal to or greater than the third threshold value.

18. The electronic device of claim 17 , wherein the memory controller is configured to decrease the capacity for providing the host data, and is configured to increase the capacity for providing the garbage collection data when the free block count of the memory blocks is equal to or less than the second threshold value.

19. The electronic device of claim 17 , wherein the memory controller is configured not to perform the garbage collection operation on the memory blocks and not to provide the garbage collection data to the non-volatile memory when the free block count of the memory blocks is equal to or greater than the first threshold value.

20. The electronic device of claim 17 wherein the memory controller is configured to increase a ratio of the capacity for providing the host data to the capacity for providing the host data and a capacity for providing the garbage collection data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2022
From: YOO, SUN-MI; LEE, YOUNG-SIK; KIM, JEONG-EUN; KIM, HYE JU; HWANG, SO DAM
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 061273/0095 →
Priority Claims (1)
KR 10-2021-0183267 · Dec 21, 2021 · national
Continuity (1)
Related Publication 20230195344A1 · Jun 22, 2023
Cited By (1)
US 12,743,239