3D MEMORY CELLS AND ARRAY ARCHITECTURES

1 . A memory cell structure, comprising:

a first semiconductor material;

a floating body semiconductor material having an internal side surface that surrounds and connects to the first semiconductor material;

a second semiconductor material having an internal side surface that surrounds and connects to the floating body semiconductor material;

a first dielectric layer connected to a top surface of the floating body material;

a second dielectric layer connected to a bottom surface of the floating body material;

a front gate connected to the first dielectric layer; and

a back gate connected to the second dielectric layer.

2 . The memory cell structure of claim 1 , wherein the first semiconductor material comprises N+ type doping, the floating body semiconductor material comprises P- type doping, and the second semiconductor material comprises N+ type doping.

3 . The memory cell structure of claim 1 , further comprising a metal line connected to the first semiconductor material.

4 . The memory cell structure of claim 1 , wherein the first semiconductor material comprises P+ type doping, the floating body semiconductor material comprises N- type doping, and the second semiconductor material comprises P+ type doping.

5 . The memory cell structure of claim 1 , wherein the first and second dielectric layers comprise one of an oxide material and a high-K material.

6 . The memory cell structure of claim 1 , wherein the first and second dielectric layers comprise charge-trapping layers.

7 . The memory cell structure of claim 6 , wherein the charge-trapping layers comprise oxide-nitride-oxide layers.

8 . A three-dimensional (3D) memory array, comprising:

a plurality of memory cells separated by a dielectric layer to form a stack of memory cells, and wherein each memory cell in the stack of memory cells comprises:

a bit line formed from one of a first semiconductor material and a first conductor material;

a floating body semiconductor material having an internal side surface that surrounds and connects to the bit line;

a source line formed from one of a second semiconductor material and a second conductor material having an internal side surface that surrounds and connects to the floating body semiconductor material;

a word line formed from a third conductor material that is coupled to the floating body semiconductor through the dielectric layer to form a gate of the memory cell; and wherein bit lines of the stack of memory cells are connected to form a vertical bit line.

9 . The three-dimensional (3D) memory array of claim 8 , wherein the array comprises multiple stacks of memory cells, and wherein word lines of the multiple stacks are connected to form multiple word line layers in a horizontal direction.

10 . The three-dimensional (3D) memory array of claim 8 , wherein the array comprises multiple stacks of memory cells, and wherein source lines of the multiple stacks are connected to form multiple source line layers in a horizontal direction.

11 . The three-dimensional (3D) memory array of claim 8 , wherein the floating body material is individual to each memory cell in the multiple stacks of memory cells.

12 . The three-dimensional (3D) memory array of claim 9 , wherein the floating body semiconductor of each memory cell is coupled to two word lines layers.

13 . The three-dimensional (3D) memory array of claim 9 , wherein the floating body semiconductor of each memory cell is coupled to one word lines layer.

14 . The three-dimensional (3D) memory array of claim 8 , wherein the first semiconductor material comprises N+ type doping, the floating body semiconductor material comprises P- type doping, and the second semiconductor material comprises N+ type doping.

15 . The three-dimensional (3D) memory array of claim 14 , further comprising a metal line connected to the first semiconductor material.

16 . The three-dimensional (3D) memory array of claim 8 , wherein the first semiconductor material comprises P+ type doping, the floating body semiconductor material comprises N- type doping, and the second semiconductor material comprises P+ type doping.

17 . The three-dimensional (3D) memory array of claim 8 , wherein the dielectric layer comprises one of an oxide material and a high-K material.

18 . The three-dimensional (3D) memory array of claim 8 , wherein the dielectric layers comprise charge-trapping layers.

19 . The three-dimensional (3D) memory array of claim 18 , wherein the charge-trapping layers comprise oxide-nitride-oxide layers.

20 . A three-dimensional (3D) memory array formed by performing operations comprising:

forming a stack of alternating layers of a first semiconductor material layer and an insulating layer;

forming multiple vertical bit line holes through the stack of alternating layers;

performing a diffusion process through the multiple vertical bit line holes to form floating bodies in each of the first semiconductor layers;

filling the multiple vertical bit line holes with a second semiconductor material to form vertical bit lines;

removing the insulating material from the stack of alternating layers;

forming a thin gate dielectric layer on surfaces of the first semiconductor material layers and the vertical bit lines;

depositing a conduct material to fill space between the first semiconductor material layers; and

etching the conductor material to form word lines.