IP Library › Granted Patent US 12,058,456
Granted Patent B2
US 12,058,456 · App. 17/939,225 · Granted Aug 6, 2024

Solid-state imaging device

Inventor: Hideo Kobayashi (Tokyo, JP)
Assignee: Canon Kabushiki Kaisha
H04N25/677H04N25/745H04N25/77H04N25/79H04N23/84
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Quick Facts
Patent No.
US 12,058,456
App. No.
17/939,225
Granted
Aug 6, 2024
Kind
B2
Abstract

A solid-state imaging device comprising: a pixel array including pixels arranged in a plurality of rows and in a plurality of columns; a first column circuit group; a second column circuit group disposed in the same side with respect to the pixel array as that in which the first column circuit group is disposed; a first counter configured to supply a count signal to the first column circuit group; and a second counter configured to supply a count signal to the second column circuit group, wherein the first column circuit group and the second column circuit group are arranged to be separate from each other in a direction along the columns, wherein the first column circuit group and the second column circuit group are configured to process pixel signals for different colors.

Claims (97)

1. A solid-state imaging device comprising:

a pixel array including pixels arranged in a plurality of rows and in a plurality of columns;

a first column circuit group;

a second column circuit group disposed in the same side with respect to the pixel array as that in which the first column circuit group is disposed;

a first counter configured to supply a count signal to the first column circuit group; and

a second counter configured to supply a count signal to the second column circuit group,

wherein the first column circuit group and the second column circuit group are arranged to be separate from each other in a direction along the columns,

wherein the first column circuit group and the second column circuit group are configured to process pixel signals for different colors.

2. The solid-state imaging device according to claim 1 ,

wherein the first column circuit group and the second column circuit group are arranged to be aligned.

3. The solid-state imaging device according to claim 1 , further comprising:

a first clock generator configured to supply a clock signal to the first counter; and

a second clock generator configured to supply a clock signal to the second counter.

4. The solid-state imaging device according to claim 1 ,

wherein the first counter is disposed substantially at a middle of the first column circuit group in a column direction, or

wherein the second counter is disposed substantially at a middle of the second column circuit group in the column direction.

5. The solid-state imaging device according to claim 1 , further comprising:

a first substrate provided with the pixel array; and

a second substrate provided with at least any of the first column circuit group, the second column circuit group, the first counter, and the second counter,

wherein the first substrate and the second substrate are stacked in layers.

6. The solid-state imaging device according to claim 1 , further comprising:

a plurality of signal processing circuits,

wherein each of the plurality of signal processing circuits includes the first column circuit group, the second column circuit group, the first counter, and the second counter.

7. An imaging system comprising:

the solid-state imaging device according to claim 1 ; and

a signal processing unit configured to process a signal output from the solid-state imaging device.

8. A moving body comprising;

the solid-state imaging device according to claim 1 ;

a moving device;

a processing device configured to acquire information from a signal output from the solid-state imaging device; and

a control device that controls the moving device on the basis of the information.

9. A solid-state imaging device comprising:

a pixel array including pixels arranged in a plurality of rows and in a plurality of columns;

a first column circuit group;

a second column circuit group disposed in the same side with respect to the pixel array as that in which the first column circuit group is disposed;

a first counter configured to supply a count signal to the first column circuit group; and

a second counter configured to supply a count signal to the second column circuit group,

wherein the first column circuit group and the second column circuit group are arranged to be separate from each other in a direction in which pixel signals are read,

wherein the first column circuit group and the second column circuit group are configured to process the pixel signals for different colors.

10. A solid-state imaging device comprising:

a pixel array including pixels arranged in a plurality of rows and in a plurality of columns; and

a plurality of signal processing circuits,

each of the plurality of signal processing circuits including:

a first column circuit group;

a second column circuit group disposed in the same side with respect to the pixel array as that in which the first column circuit group is disposed;

a first counter configured to supply a count signal to the first column circuit group; and

a second counter configured to supply a count signal to the second column circuit group,

wherein the first column circuit group and the second column circuit group are arranged to be separate from each other in a direction along the columns,

wherein, in at least one of the plurality of signal processing circuits, the first column circuit group, the second column circuit group, the first counter, and the second counter are located between a plurality of scanning circuits each of which scans the plurality of pixels in each of the rows.

11. The solid-state imaging device according to claim 10 ,

wherein the first column circuit group and the second column circuit group are arranged to be aligned.

12. The solid-state imaging device according to claim 10 ,

wherein each of the plurality of signal processing circuits further includes:

a first clock generator configured to supply a clock signal to the first counter; and

a second clock generator configured to supply a clock signal to the second counter.

13. The solid-state imaging device according to claim 10 ,

wherein, in at least one of the plurality of the signal processing circuits, the first counter is disposed substantially at a middle of the first column circuit group in a column direction, or

wherein the second counter is disposed substantially at a middle of the second column circuit group in the column direction.

14. The solid-state imaging device according to claim 10 , further comprising:

a first substrate provided with the pixel array; and

a second substrate provided with the plurality of signal processing circuits,

wherein the first substrate and the second substrate are stacked in layers.

15. An imaging system comprising:

the solid-state imaging device according to claim 10 ; and

a signal processing unit configured to process a signal output from the solid-state imaging device.

16. A moving body comprising;

the solid-state imaging device according to claim 10 ;

a moving device;

a processing device configured to acquire information from a signal output from the solid-state imaging device; and

a control device configured to control the moving device on the basis of the information.

17. The solid-state imaging device according to claim 1 ,

wherein the pixel array includes a first pixel and a second pixel,

wherein the first pixel and the second pixel are arranged in different columns,

wherein the first column circuit group includes a plurality of first column circuits,

wherein the second column circuit group includes a plurality of second column circuits,

wherein the first pixel is electrically connectable to at least one of the plurality of first column circuits,

wherein the second pixel is electrically connectable to at least one of the plurality of second column circuits, and

wherein said at least one of the plurality of first column circuits and said one at least one of the plurality of second column circuits are arranged in a same column.

18. The solid-state imaging device according to claim 1 ,

wherein the first column circuit group is configured to process pixel signals for only a first color, and

wherein the second column circuit group is configured to process pixel signals for only a second color.

19. The solid-state imaging device according to claim 9 ,

wherein the pixel array includes a first pixel and a second pixel,

wherein the first pixel and the second pixel are arranged in different columns,

wherein the first column circuit group includes a plurality of first column circuits,

wherein the second column circuit group includes a plurality of second column circuits,

wherein the first pixel is electrically connectable to at least one of the plurality of first column circuits,

wherein the second pixel is electrically connectable to at least one of the plurality of second column circuits, and

wherein said at least one of the plurality of first column circuits and said at least one of the plurality of second column circuits are arranged in a same column.

20. The solid-state imaging device according to claim 10 ,

wherein the pixel array includes a first pixel and a second pixel,

wherein the first pixel and the second pixel are arranged in different columns,

wherein the first column circuit group includes a plurality of first column circuits,

wherein the second column circuit group includes a plurality of second column circuits,

wherein the first pixel is electrically connectable to at least one of the plurality of first column circuits,

wherein the second pixel is electrically connectable to at least one of the plurality of second column circuits, and

wherein said at least one of the plurality of first column circuits and said at least one of the plurality of second column circuits are arranged in a same column.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2022
From: KOBAYASHI, HIDEO
To: CANON KABUSHIKI KAISHA
Reel/Frame 061383/0643 →
Priority Claims (1)
JP 2021-146388 · Sep 8, 2021 · national
Continuity (1)
Related Publication 20230072715A1 · Mar 9, 2023