Silicon carbide substrate including multiple semiconductor layers having a high break down voltage
In a silicon carbide substrate including: a SiC substrate; and a first semiconductor layer, a second semiconductor layer and a drift layer that are epitaxial layers sequentially formed on the SiC substrate, an impurity concentration of the first semiconductor layer is lower than impurity concentrations of the SiC substrate and the second semiconductor layer, and the second semiconductor layer is formed to have a high impurity concentration or a large thickness.
1 . A silicon carbide substrate comprising:
a first substrate having a predetermined conductive type and containing silicon carbide;
a first semiconductor layer having the conductive type and containing silicon carbide, on the first substrate;
a second semiconductor layer having the conductive type and containing silicon carbide, on the first semiconductor layer; and
a third semiconductor layer having the conductive type and containing silicon carbide, on the second semiconductor layer,
wherein the first semiconductor layer is in contact with an upper surface of the first substrate,
wherein a first impurity concentration of the first semiconductor layer is lower than both a second impurity concentration of the second semiconductor layer and a fourth impurity concentration of the upper surface of the first substrate,
wherein the first impurity concentration is higher than a third impurity concentration of the third semiconductor layer,
wherein the fourth impurity concentration is higher than the second impurity concentration,
wherein the second impurity concentration N 2 [cm −3 ], a thickness W 2 [μm] of the second semiconductor layer and a rated voltage Vn [V] of an element formed on the silicon carbide substrate satisfy a condition expressed by the following equation (1);
W 2≥(−2.69×10 12 ln( Vn )+2.22×10 13 ) N 2 −0.65 (1);
wherein a thickness of the first semiconductor layer is greater than 1 μm and less than 2 μm,
wherein the second semiconductor layer attenuates minority carriers injected into the third semiconductor layer, and
wherein the rated voltage Vn is 1700 V or more.
2 . The silicon carbide substrate according to claim 1 ,
wherein the first impurity concentration is higher than 1×10 16 cm −3 and equal to or lower than 1×10 17 cm −3 .
3 . A silicon carbide substrate comprising:
a first substrate having a predetermined conductive type and containing silicon carbide;
a first semiconductor layer having the conductive type and containing silicon carbide, on the first substrate;
a second semiconductor layer having the conductive type and containing silicon carbide, on the first semiconductor layer; and
a third semiconductor layer having the conductive type and containing silicon carbide, on the second semiconductor layer,
wherein the first semiconductor layer is in contact with an upper surface of the first substrate,
wherein a first impurity concentration of the first semiconductor layer is lower than both a second impurity concentration of the second semiconductor layer and a fourth impurity concentration of the upper surface of the first substrate,
wherein the first impurity concentration is higher than a third impurity concentration of the third semiconductor layer,
wherein the fourth impurity concentration is higher than the second impurity concentration,
wherein the second impurity concentration N 2 [cm −3 ], a thickness W 2 [μm] of the second semiconductor layer and a rated voltage Vn [V] of an element formed on the silicon carbide substrate satisfy a condition expressed by the following equation (2);
W 2≥(−2.53×10 12 ln( Vn )+2.16×10 13 ) N 2 −0.65 (2);
wherein a thickness of the first semiconductor layer is greater than 1 μm and less than 2 μm,
wherein the second semiconductor layer attenuates minority carriers injected into the third semiconductor layer, and
wherein the rated voltage Vn is 1700 V or more.
4 . The silicon carbide substrate according to claim 3 ,
wherein the first impurity concentration is higher than 1×10 16 cm −3 and equal to or lower than 1×10 17 cm −3 .
5 . A silicon carbide substrate comprising:
a first substrate having a predetermined conductive type and containing silicon carbide;
a first semiconductor layer having the conductive type and containing silicon carbide, on the first substrate;
a second semiconductor layer having the conductive type and containing silicon carbide, on the first semiconductor layer; and
a third semiconductor layer having the conductive type and containing silicon carbide, on the second semiconductor layer,
wherein the first semiconductor layer is in contact with an upper surface of the first substrate,
wherein a first impurity concentration of the first semiconductor layer is lower than both a second impurity concentration of the second semiconductor layer and a fourth impurity concentration of the upper surface of the first substrate,
wherein the first impurity concentration is higher than a third impurity concentration of the third semiconductor layer,
wherein the fourth impurity concentration is higher than the second impurity concentration,
wherein the second impurity concentration N 2 [cm −3 ], a thickness W 2 [μm] of the second semiconductor layer and the maximum current density J [A/cm 2 ] in usage of an element formed on the silicon carbide substrate satisfy a condition expressed by the following equation (3);
W 2≥(2.52×10 12 ln( J )−1.31×10 13 ) N 2 −0.65 (3);
wherein a thickness of the first semiconductor layer is greater than 1 μm and less than 2 μm,
wherein the second semiconductor layer attenuates minority carriers injected into the third semiconductor layer, and
wherein the maximum current density J is 200 A/cm 2 or more.
6 . The silicon carbide substrate according to claim 5 ,
wherein the first impurity concentration is higher than 1×10 16 cm −3 and equal to or lower than 1×10 17 cm −3 .