Delaying interrupts for virtual machines
A computing device can detect an interrupt associated with a virtual machine. Based on detecting the interrupt, the computing device can determine whether the virtual machine is in an idle state. Based on determining that the virtual machine is in the idle state, the computing device can delay the interrupt by storing the interrupt in an interrupt register for a period of time and preventing the interrupt from being transmitted to the virtual machine during the period of time. After storing the interrupt in the interrupt register, the computing device can determine that the virtual machine is in an awake state. In response to determining that the virtual machine is in the awake state, the computing device can transmit the interrupt from the interrupt register to the virtual machine.
1 . A non-transitory computer-readable medium comprising program code that is executable by a processor to:
detect a first interrupt associated with a first device, wherein the first interrupt is intended for a virtual machine;
based on detecting the first interrupt:
determine whether the virtual machine is in an idle state;
determine that a first device type associated with the first device is on a list of device types for which interrupts are to be delayed at least until the virtual machine is awakened by an event other than the first interrupt; and
based on determining that the virtual machine is in the idle state, and that the first device type is on the list of device types for which interrupts are to be delayed at least until the virtual machine is awakened by an event other than the first interrupt, delay the first interrupt by storing the first interrupt in an interrupt register and preventing the first interrupt from being transmitted to the virtual machine at least until the virtual machine is awakened by an event other than the first interrupt, such that the first interrupt is not used as a basis for awakening the virtual machine from the idle state;
subsequent to storing the first interrupt in the interrupt register to delay delivery of the first interrupt to the virtual machine:
determine that the virtual machine is in an awake state; and
in response to determining that the virtual machine is in the awake state, release the delay by transmitting the first interrupt from the interrupt register to the virtual machine, thereby ending the delay of the first interrupt;
detect a second interrupt associated with a second device that is different from the first device, wherein the second interrupt is also intended for the virtual machine;
determine that a second device type associated with the second device is not on the list of device types for which interrupts are to be delayed; and
based on determining that the second device type is not on the list of device types for which interrupts are to be delayed, transmit the second interrupt to the virtual machine without delaying the second interrupt and without storing the second interrupt in the interrupt register.
2 . The non-transitory computer-readable medium of claim 1 , wherein the interrupt register is located in a memory area for a hypervisor configured to manage the virtual machine.
3 . The non-transitory computer-readable medium of claim 1 , wherein the first interrupt is associated with adding the first device to the virtual machine.
4 . The non-transitory computer-readable medium of claim 1 , wherein the first interrupt is associated with removing the first device from the virtual machine.
5 . The non-transitory computer-readable medium of claim 2 , wherein the interrupt register is a posted interrupt register of a virtual central processing unit associated with the virtual machine.
6 . The non-transitory computer-readable medium of claim 1 , further comprising program code that is executable by the processor to:
in response to detecting the second interrupt, determine that the virtual machine is in the awake state.
7 . The non-transitory computer-readable medium of claim 1 , wherein the virtual machine transitions from the idle state to the awake state independently of the first interrupt.
8 . A method comprising:
detecting, by a processor, a first interrupt associated with a first device, wherein the first interrupt is intended for a virtual machine;
based on detecting the first interrupt:
determining, by the processor, whether the virtual machine is in an idle state;
determining, by the processor, that a first device type associated with the first device is on a list of device types for which interrupts are to be delayed at least until the virtual machine is awakened by an event other than the first interrupt; and
based on determining that the virtual machine is in the idle state, and that the first device type is on the list of device types for which interrupts are to be delayed at least until the virtual machine is awakened by an event other than the first interrupt, delaying, by the processor, the first interrupt by storing the first interrupt in an interrupt register and preventing the first interrupt from being transmitted to the virtual machine at least until the virtual machine is awakened by an event other than the first interrupt, such that the first interrupt is not used as a basis for awakening the virtual machine from the idle state;
subsequent to storing the first interrupt in the interrupt register to delay delivery of the first interrupt to the virtual machine:
determining, by the processor, that the virtual machine is in an awake state; and
in response to determining that the virtual machine is in the awake state, releasing, by the processor, the delay by transmitting the first interrupt from the interrupt register to the virtual machine, thereby ending the delay of the first interrupt;
detecting, by the processor, a second interrupt associated with a second device that is different from the first device, wherein the second interrupt is also intended for the virtual machine;
determining, by the processor, that a second device type associated with the second device is not on the list of device types for which interrupts are to be delayed; and
based on determining that the second device type is not on the list of device types for which interrupts are to be delayed, transmitting, by the processor, the second interrupt to the virtual machine without delaying the second interrupt and without storing the second interrupt in the interrupt register.
9 . The method of claim 8 , wherein the first interrupt is associated with adding the first device to the virtual machine.
10 . The method of claim 8 , wherein the first interrupt is associated with removing the first device from the virtual machine.
11 . The method of claim 9 , wherein the interrupt register is a posted interrupt register of a virtual central processing unit associated with the virtual machine.
12 . The method of claim 8 , further comprising:
in response to detecting the second interrupt, determining, by the processor, that the virtual machine is in the awake state.
13 . The method of claim 8 , wherein the virtual machine transitions from the idle state to the awake state independently of the first interrupt.
14 . The method of claim 8 , further comprising:
detecting a transition of the virtual machine from the idle state to the awake state; and
in response to detecting the transition of the virtual machine from the idle state to the awake state, releasing the delay of the first interrupt by transmitting the first interrupt from the interrupt register to the virtual machine.
15 . A system comprising:
a processor; and
a memory comprising instructions that are executable by the processor to:
detect a first interrupt associated with a first device, wherein the first interrupt is intended for a virtual machine;
based on detecting the first interrupt:
determine whether the virtual machine is in an idle state;
determine that a first device type associated with the first device is on a list of device types for which interrupts are to be delayed at least until the virtual machine is awakened by an event other than the first interrupt; and
based on determining that the virtual machine is in the idle state, and that the first device type is on the list of device types for which interrupts are to be delayed at least until the virtual machine is awakened by an event other than the first interrupt, delay the first interrupt by storing the first interrupt in an interrupt register and preventing the first interrupt from being transmitted to the virtual machine at least until the virtual machine is awakened by an event other than the first interrupt, such that the first interrupt is not used as a basis for awakening the virtual machine from the idle state;
subsequent to storing the first interrupt in the interrupt register to delay delivery of the first interrupt to the virtual machine:
determine that the virtual machine is in an awake state; and
in response to determining that the virtual machine is in the awake state, release the delay by transmitting the first interrupt from the interrupt register to the virtual machine, thereby ending the delay of the first interrupt;
detect a second interrupt associated with a second device that is different from the first device, wherein the second interrupt is also intended for the virtual machine;
determine that a second device type associated with the second device is not on the list of device types for which interrupts are to be delayed; and
based on determining that the second device type is not on the list of device types for which interrupts are to be delayed, transmit the second interrupt to the virtual machine without delaying the second interrupt and without storing the second interrupt in the interrupt register.
16 . The system of claim 15 , wherein the interrupt register is located in a memory area for a hypervisor configured to manage the virtual machine.
17 . The system of claim 15 , wherein the first interrupt is associated with adding the first device to the virtual machine.
18 . The system of claim 15 , wherein the first interrupt is associated with removing the first device from the virtual machine.
19 . The system of claim 16 , wherein the interrupt register is a posted interrupt register of a virtual central processing unit associated with the virtual machine.
20 . The system of claim 16 , wherein the virtual machine transitions from the idle state to the awake state independently of the first interrupt.