Bit-flipping decoder and decoding method for irregular codes

1. A method of operating a bit-flipping decoder, comprising:

receiving a signal comprising a noisy codeword transmitted over a noisy channel in a data storage system, the codeword having been generated based on a parity check matrix of a low-density parity-check (LDPC) code and provided to a communication channel of the data storage system prior to reception by the bit-flipping decoder; and

performing a single decoding iteration on the received noisy codeword, the single decoding iteration spanning a plurality of stages,

wherein, performing the single decoding iteration includes, for each of the plurality of stages:

computing a flipping energy corresponding to a single column of the parity check matrix,

flipping at least one bit in the single column upon a determination that the flipping energy exceeds a flipping threshold,

computing, subsequent to the flipping, a syndrome as a product of the noisy codeword and the parity check matrix, and

updating the flipping threshold upon a determination that the syndrome is not zero, wherein updating the flipping threshold for a first stage of the plurality of stages is based on a first set of rules, and wherein updating the flipping threshold for a second stage subsequent to the first stage is based on a second set of rules different from the first set of rules,

wherein the flipping threshold is updated in a middle of the single decoding iteration and thereby increases a throughput of the bit-flipping decoder, and

wherein the flipping energy is determined based on:

a weight of at least one check node coupled to the column;

a syndrome as a product of the noisy codeword and the parity check matrix; and

a hard decision value of a previous iteration and a channel output value associated with the column.

2. The method of claim 1 , wherein the flipping energy is computed based on a product of the weight and the syndrome and a logical operation of the hard decision value and the channel output value.

3. The method of claim 2 , wherein the flipping energy is computed based on an addition of the product of the weight and the syndrome and the logical operation.

4. The method of claim 2 , wherein the logical operation includes an exclusive OR (XOR) operation.

5. The method of claim 1 , wherein the weight has a higher value as the check node is strong.

6. The method of claim 1 , wherein the weight is determined based on a row weight of the check node and a column weight profile of the column.

7. The method of claim 1 , wherein the weight is determined based on a row weight of the check node, a column weight profile of the column and a number of the decoding iteration.

8. The method of claim 1 , wherein updating the flipping threshold is based on an index of the decoding iteration, a number of non-zero values in the syndrome, or a number of bits flipped in a column of the parity check matrix in a previous decoding iteration.

9. The method of claim 1 , wherein one or both of the first set and the second set of rules comprises a finite state machine (FSM) to maximize a throughput of the bit-flipping decoder.

10. The method of claim 1 , wherein flipping the at least one bit comprises flipping multiple bits in the single column,

each stage of the plurality of stages corresponds to a predetermined number of clock cycles, and

an index of the single decoding iteration is less than a maximum number of decoding iterations.

11. A decoding system comprising:

a processor and a memory including instructions stored thereupon, wherein the instructions upon execution by the processor cause a bit-flipping decoder to:

receive a signal comprising a noisy codeword transmitted over a noisy channel in a data storage system, the codeword having been generated based on a parity check matrix of a low-density parity-check (LDPC) code and provided to a communication channel of the data storage system prior to reception by the bit-flipping decoder; and

perform a single decoding iteration on the received noisy codeword, the single decoding iteration spanning a plurality of stages,

wherein, performing the single decoding iteration includes, for each of the plurality of stages:

computing a flipping energy corresponding to a single column of the parity check matrix,

flipping at least one bit in the single column upon a determination that the flipping energy exceeds a flipping threshold,

computing, subsequent to the flipping, a syndrome as a product of the noisy codeword and the parity check matrix, and

updating the flipping threshold upon a determination that the syndrome is not zero, wherein updating the flipping threshold for a first stage of the plurality of stages is based on a first set of rules, and wherein updating the flipping threshold for a second stage subsequent to the first stage is based on a second set of rules different from the first set of rules, and

wherein the flipping threshold is updated in a middle of the single decoding iteration and thereby increases a throughput of the bit-flipping decoder, and

wherein the flipping energy is determined based on:

a weight of at least one check node coupled to the column;

a syndrome as a product of the noisy codeword and the parity check matrix; and

a hard decision value of a previous iteration and a channel output value associated with the column.

12. The system of claim 11 , wherein the flipping energy is computed based on a product of the weight and the syndrome and a logical operation of the hard decision value and the channel output value.

13. The system of claim 12 , wherein the flipping energy is computed based on an addition of the product of the weight and the syndrome and the logical operation.

14. The system of claim 12 , wherein the logical operation includes an exclusive OR (XOR) operation.

15. The system of claim 11 , wherein the weight has a higher value as the check node is strong.

16. The system of claim 11 , wherein the weight is determined based on a row weight of the check node and a column weight profile of the column.

17. The system of claim 11 , wherein the weight is determined based on a row weight of the check node, a column weight profile of the column and a number of the decoding iteration.

18. The system of claim 11 , wherein updating the flipping threshold is based on an index of the decoding iteration, a number of non-zero values in the syndrome, or a number of bits flipped in a column of the parity check matrix in a previous decoding iteration.

19. The system of claim 11 , wherein one or both of the first set and the second set of rules comprises a finite state machine (FSM) to maximize a throughput of the bit-flipping decoder.

20. The system of claim 11 , wherein flipping the at least one bit comprises flipping multiple bits in the single column,

each stage of the plurality of stages corresponds to a predetermined number of clock cycles, and

an index of the single decoding iteration is less than a maximum number of decoding iterations.