Liquid crystal display device
To prevent a phenomenon that an alignment film material is difficult to flow into the through-hole where a diameter of a through-hole for connecting between a pixel electrode and a source electrode is reduced. A liquid crystal display device comprising a TFT substrate having pixels each including a common electrode formed on an organic passivation film, an interlayer insulating film formed so as to cover the common electrode, a pixel electrode having a slit and formed on the interlayer insulating film, a through-hole formed in the organic passivation film and the interlayer insulating film, and a source electrode electrically conducted to the pixel electrode via the through-hole. A taper angle at a depth of D/2 of the through-hole is equal to or more than 50 degrees. The pixel electrode covers part of a side wall of the through-hole but does not cover the remaining part of the side wall of the through-hole. This configuration facilitates the alignment film material to flow into the through-hole, thereby solving a thickness unevenness of the alignment film in vicinity of the through-hole.
1. A liquid crystal display device comprising:
a transistor substrate including;
a thin film transistor having a source electrode,
an organic insulating film formed on the thin film transistor, the organic insulating film having a through-hole,
a common electrode formed on the organic insulating film,
an interlayer insulating film formed on the common electrode, and
a pixel electrode formed on the interlayer insulating film, the pixel electrode having a slit and connected to the source electrode through the through-hole;
a counter substrate having a black matrix formed thereon; and
liquid crystal sandwiched between the transistor substrate and the counter substrate; wherein
an end of the slit is located in the through hole and overlaps the black matrix in a plan view.
2. The liquid crystal display device according to claim 1 , wherein
the through hole has a side wall that is tapered from a bottom face of the through-hole, which is at a bottom surface side of the organic insulating film, and
the end of the slit is located on the side wall of the through-hole.
3. The liquid crystal display device according to claim 1 , wherein
the pixel electrode extends over the bottom face of the through hole up to an end of the slit, and
the end of the slit overlaps with the black matrix in a plan view.
4. The liquid crystal display device according to claim 1 , further comprising a scanning line driving the thin film transistor, and
a video signal line electrically connected to the source electrode,
wherein the scanning line extends in a first direction, and
the video signal line extends in a second direction crossing the first direction.
5. The liquid crystal display device according to claim 4 , wherein
a bottom face of the through hole is between the gate line and the slit of the pixel electrode in a plan view.
6. The liquid crystal display device according to claim 1 , wherein
the transistor substrate further includes an alignment layer, and
a part of the through-hole is covered with the alignment layer via the pixel electrode, and a remaining part of the through-hole is directly covered with the alignment layer.
7. The liquid crystal display device according to claim 6 , wherein
the alignment layer consists of a photo-alignment film.
8. The liquid crystal display device according to claim 1 , wherein
a side wall of the through-hole is covered with the interlayer insulating film.
9. The liquid crystal display device according to claim 8 , wherein
the interlayer insulating film directly contacts with the source electrode.
10. The liquid crystal display device according to claim 1 , wherein
a part of an outer edge of the pixel electrode does not overlap the common electrode.
11. The liquid crystal display device according to claim 10 , wherein
the through hole has a side wall that is tapered from a bottom face of the through-hole, and
the bottom face of the through-hole is located between the end of the slit and the part of an outer edge of the pixel electrode in a plan view.