IP Library › Granted Patent US 11,974,435
Granted Patent B2
US 11,974,435 · App. 17/947,862 · Granted Apr 30, 2024

Semiconductor device and manufacturing method of a semiconductor device

Inventor: In Su Park (Icheon-si, KR)
Assignee: SK hynix Inc.
H10B43/27H01L29/1037H01L29/41741H01L29/456H10B41/27H10B63/845H01L21/02236H01L21/02532H01L21/02636H01L21/31144H01L21/32139H01L29/40114H01L29/40117
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Quick Facts
Patent No.
US 11,974,435
App. No.
17/947,862
Granted
Apr 30, 2024
Kind
B2
Abstract

A semiconductor device includes a stack structure, a channel layer passing through the stack structure, a memory layer enclosing the channel layer and including first and second openings which expose the channel layer, a well plate coupled to the channel layer through the first opening, and a source plate coupled to the channel layer through the second opening.

Claims (11)

1. A semiconductor device, comprising:

a lower structure including a well region and a source region, wherein the well region and the source region are separated from each other;

a stack structure, over the lower structure, including conductive layers and first insulating layers alternately stacked with each other;

a channel layer passing through the stack structure and coupled to the lower structure, wherein the channel layer is coupled to the well region and the source region; and

a source connection structure physically contacted with the source region.

2. The semiconductor device of claim 1 , further comprising a well connection structure physically contacted with the well region.

3. The semiconductor device of claim 1 , further comprising an insulating pattern insulating the source connection structure from the well region.

4. The semiconductor device of claim 1 , further comprising a slit insulating structure separating the stack structure and a portion of the lower structure into a first region and a second region.

5. The semiconductor device of claim 4 , wherein the well connection structure is included in the first region.

6. The semiconductor device of claim 4 , wherein the source connection structure and the channel layer are included in the second region.

7. The semiconductor device of claim 4 , wherein another portion of the lower structure is coupled between the first region and the second region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2022
From: PARK, IN SU
To: SK HYNIX INC.
Reel/Frame 061140/0376 →
Priority Claims (1)
KR 10-2018-0093830 · Aug 10, 2018 · national
Continuity (3)
Continuation 17091180 · Nov 6, 2020
Continuation 16359568 · Mar 20, 2019
Related Publication 20230018490A1 · Jan 19, 2023